R

Ramya BK

Software Engineer

Mangaluru, Karnataka, India6 yrs 11 mos experience

Key Highlights

  • Expert in Functional Verification methodologies.
  • Proficient in SystemVerilog and UVM.
  • Strong background in low power verification techniques.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationSystemverilogUniversal Verification Methodology (uvm)

Other Skills

Functional SafetyAXIPhase-Locked Loop (PLL)FLLSVAGLSPerllow power verificationAMBAVerilog

Experience

6 yrs 11 mos
Total Experience
--
Average Tenure
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Current Experience

Synopsys inc

2 roles

ASIC Digital Design,Staff Engineer

Promoted

Jan 2024 – Present · 2 yrs 5 mos · India

Functional SafetyFunctional VerificationAXIPhase-Locked Loop (PLL)FLLSVA+7

ASIC Digital Design Engineer,II

Jun 2022 – Dec 2023 · 1 yr 6 mos · India

AMBAFunctional Verification

Insemi technology services pvt. ltd.(amd)

Design Verification Engineer

Jun 2019 – Jun 2022 · 3 yrs · India · On-site

Universal Verification Methodology (UVM)low power verification

Education

Bangalore University

UVCE

Visvesvaraya Technological University

Canara Engineering College

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