Thapaswi Gowda — Director of Engineering
5+years of Semiconductor industry experience memory Layouts and analog layouts Worked on technology nodes: 28nm, 20nm,1.8nm,14nm Latest technology like GAA and FINFET Hands on experience with Bulk CMOS Expertise in DRC, LVS, ERC, EM IR, FM issues like Antenna, Lathcup.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI layout and automation.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 4 mos
Skills
- Technical Leadership
- Layout Design
Career Highlights
- 5+ years of experience in the Semiconductor industry.
- Expertise in advanced technology nodes including GAA and FINFET.
- Proficient in DRC, LVS, ERC, and EM IR issues.
Work Experience
HCLTech
Technical Lead (1 mo)
Lead Engineer ( Memory Layout ) (1 yr 6 mos)
Wipro
Senior Project Engineer (1 yr 11 mos)
ACL Digital
Layout engineer ( Hardware engineer) (7 mos)
LEAFKITE TECHNOLOGIES(INDIA)
Layout Engineer (2 yrs 6 mos)
Education
Bachelor of Engineering - BE at Visvesvaraya Technological University
diploma at BET Polytechnic