Trí Võ Minh

Software Engineer

Ho Chi Minh City, Vietnam1 yr 9 mos experience

Key Highlights

5 years of experience in layout design.
Expert in Analog Mixed Signal IC design.
Trained and mentored interns and new team members.

Stackforce AI infers this person is a Semiconductor Layout Engineer with expertise in Analog Mixed Signal design.

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Skills

Core Skills

Layout DesignAnalog Mixed Signal DesignMixed-signal Ic Design

Other Skills

Cadence Virtuoso Layout EditorDesign Rule Checking (DRC)Synopsys toolsDebuggingDocumentationBash scriptLinuxMicrosoft OfficeCustom CompilerLayout effectsAnalog Circuit DesignElectronicsIC LayoutC (Programming Language)Integrated Circuits (IC)

About

I am a Layout Design Engineer who graduated from Ho Chi Minh University of Technology, having 5 years' experience at Synopsys Vietnam and currently working at Marvell Singapore as an Analog Mixed Signal Layout Design Engineer. Being from a supporter to a lead of IPs, I gained crucial skills and knowledge in layout design of Die-to-die interface (HBM and UCIE technologies) and valuable experiences with technology processes such as 12nm, 5nm, and 3nm. Feel free to send me a message if you would like to know more about me. I am always eager to hear from others and expand my network on LinkedIn. Specialties: Synopsys tools, Bash script, Linux, Microsoft Office, Cadence Virtuoso, ...

Experience

1 yr 9 mos

Total Experience

Average Tenure

Current Experience

Marvell technology

Senior Layout Engineer

May 2025 – Present · 1 yr 1 mo · Singapore · On-site

Cadence Virtuoso Layout EditorDesign Rule Checking (DRC)Layout DesignAnalog Mixed Signal Design

Synopsys inc

2 roles

Staff Layout Engineer

Feb 2025 – Aug 2025 · 6 mos · Vietnam

Senior Layout Engineer

Oct 2020 – Feb 2025 · 4 yrs 4 mos · Vietnam

At Synopsys, I fortunately joined a team taking responsibility for UCIe IP Solutions. Synopsys’ complete Universal Chiplet Interconnect Express (UCIe) IP solution includes controller, PHY, and verification IP. The PHY in advanced FinFET processes offers high-bandwidth, low-power, and low-latency die-to-die connectivity in a package.
My contributions:
Cooperating closely with the Circuit Designers and designing layouts that satisfied the circuit’s requirements, DRC, layout effects, and more. This means I am responsible for my layout design and have a deep understanding of what I am working on.
Taking the role of a trainer for the internship program. Training interns to prepare them to become valuable team members is crucial, and I dedicated myself to this job.
Mentoring new members to catch up on project knowledge and processes.
Preparing documents and notes for each release.
Debugging to find out the root causes of the issue and how to solve them.
Remotely working with international colleagues by assigning tasks and giving guidelines.
Including in the process of building a workflow for my team.
Participating in the process of researching and testing the applicability of new tools to improve the productivity of layout designers and present to the whole team.