R

Ruhani Goyal

Product Manager

Patiala, Punjab, India3 yrs 7 mos experience

Key Highlights

  • Lead role in validating EDA products
  • Cadence-certified in extraction methodologies
  • Strong collaboration with R&D and product teams
Stackforce AI infers this person is a VLSI Design and EDA expert focused on semiconductor validation.

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Skills

Core Skills

Vlsi DesignEda

Other Skills

Virtuoso Schematic EditorParasitic ExtractionCadence SpectreQuantusEldoCadence Virtuoso Layout EditorPerlVerilogPython (Programming Language)UnixXilinx ISELTSpiceCadence Virtuoso

About

I am a Lead Product Validation Engineer at Cadence Design Systems with 3 years of experience, backed by an M.Tech in VLSI Design. I work on validating transistor-level EDA products, ensuring accuracy, performance, and customer readiness across advanced and mature technology nodes. My expertise spans Virtuoso, Spectre, and Quantus Parasitic Extraction, with hands-on experience in building validation flows, executing large-scale regressions, debugging complex issues, and enabling high-quality product releases. I have played a key role in validating critical features while collaborating closely with R&D, product management, and customer-facing teams. Previously, I completed a one-year internship at STMicroelectronics, gaining strong exposure to analog and mixed-signal design and verification. I am also Cadence-certified (Quantus Transistor-Level T1 v23.1), reflecting my proficiency with industry-leading extraction methodologies. As a Lead, I focus on technical ownership, mentoring engineers, and driving validation excellence, while continuously strengthening my expertise in VLSI design and EDA. I am passionate about delivering robust, scalable solutions that advance the semiconductor industry.

Experience

3 yrs 7 mos
Total Experience
--
Average Tenure
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Current Experience

Cadence

3 roles

Lead Product Validation Engineer

Promoted

Jan 2026Present · 5 mos · Noida, Uttar Pradesh, India

Virtuoso Schematic EditorParasitic ExtractionCadence SpectreQuantusVLSI DesignEDA

Product Validation Engineer ll

Oct 2022Dec 2025 · 3 yrs 2 mos · Noida, Uttar Pradesh, India

Parasitic ExtractionVLSI Design

Product Validation Intern

Jul 2022Oct 2022 · 3 mos · Noida, Uttar Pradesh, India

Quantus

Stmicroelectronics

Intern

Jul 2021Jun 2022 · 11 mos · India, Greater Noida, Uttar Pradesh

EldoCadence Virtuoso Layout Editor

Education

Thapar Institute of Engineering & Technology

Masters of Technology — VLSI Design

Jan 2020Jan 2022

Punjabi University

Bachelor of Technology - B.Tech — Electronics and Communication Engineering

Jan 2015Jan 2019

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