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Ayush Pathak

Software Engineer

Bengaluru, Karnataka, India4 yrs 8 mos experience

Key Highlights

  • Expert in Design Verification with hands-on experience.
  • Proficient in System on a Chip (SoC) and verification methodologies.
  • Strong background in digital and analog electronics.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in design and verification methodologies.

Contact

Skills

Core Skills

System On A Chip (soc)VerificationDdr4Power ManagementAi WorkloadsDesign VerificationProgramming

Other Skills

System Verilog AssertionsAXIEthernetTest PlansDebuggingPython (Programming Language)VerilogVery-Large-Scale Integration (VLSI)ToggleSystems AnalysisAMBA AHBDDR2DDR3 SDRAMDDR SDRAMService Provider Interface (SPI)

About

An enthusiastic spirit with highly motivated and leadership skills. Professionally trained Design Verification Engineer. • High level understanding and knowledge in Verilog, SystemVerilog, SystemVerilog Assertion, Electronics Circuit Design, Digital Electronics, Analog Electronics, Universal Verification Methodology (UVM), DFT. • Hands on experience in developing test bench components. • Strong quality assurance professional with a Bachelor of Technology - BTech focused in Electronics and Communications Engineering from ABES Engineering College.

Experience

4 yrs 8 mos
Total Experience
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Average Tenure
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Current Experience

Hcltech

Lead Engineer

Oct 2025Present · 8 mos · Noida · Remote

Qualcomm

Verification Engineer 2

Mar 2025Oct 2025 · 7 mos

  • I worked on verification for the Turing subsystem, where I verified multiple modules within the subsystem and also had the opportunity to work on formal verification
System on a Chip (SoC)System Verilog AssertionsAXIEthernetVerification

Incise infotech private limited

Verification Engineer

Apr 2024Sep 2025 · 1 yr 5 mos · Noida, Uttar Pradesh, India · On-site

  • Verified the DDR4 memory controller for the ODC project at Andes Technology, ensuring compliance with JEDEC standards and robust integration with system components.
  • Developed and executed detailed test plans and directed/constraint-random test cases to validate read/write operations, initialization sequences, and timing parameters.
  • Performed debug and root-cause analysis using simulation waveforms and logs to resolve functional issues in the memory subsystem.

Nxp semiconductors

Verification Engineer

Apr 2024Mar 2025 · 11 mos · Noida, Uttar Pradesh, India · On-site

  • Worked on Clock, Reset, and Power Management (CRPM) for Flexible SubSystem (FSS) and Common SubSystem (CoSS), focusing on low-power design and efficient system integration. Contributed to the development and validation of CRPM infrastructure, collaborating with architecture, RTL, and verification teams to implement power optimization techniques such as power gating, clock gating, and DVFS. Supported bring-up and debugging on pre-silicon platforms using simulation, emulation, and hardware prototypes.
Python (Programming Language)DDR4DebuggingVerilogVery-Large-Scale Integration (VLSI)Ethernet+2

Synopsys inc

Graduate Engineering Trainee

Nov 2022Apr 2024 · 1 yr 5 mos · Bengaluru, Karnataka, India · On-site

  • Successfully verified the ARCSync module, designed to accelerate AI workloads by enabling synchronization across multiple ARC processors.
  • Developed and executed comprehensive test cases, achieving full functional and code coverage for the module.
  • Verified all key features of ARCSync, including synchronization mechanisms and AI acceleration support, along with thorough validation of the Power Management Unit (PMU).
ToggleSystems AnalysisAXIEthernetDebuggingAMBA AHB+7

Maven silicon

Trainee at Maven Silicon, Bangalore

Apr 2022Nov 2022 · 7 mos · Bengaluru, Karnataka, India

  • Completed Advance Design and Verification course. Hands on experience on 2 major projects: Router 1X3 packet design based protocol and Dual ported RAM(DPRAM) respectively.
C (Programming Language)Python (Programming Language)SystemVerilogSystem Verilog AssertionsUniversal Verification Methodology (UVM)Digital Electronics+8

Truechip solutions

Electronic Engineer

Nov 2020Dec 2021 · 1 yr 1 mo · Noida, Uttar Pradesh, India

  • Completed CEP VLSI course.
C (Programming Language)Python (Programming Language)Universal Verification Methodology (UVM)Analog Circuit DesignDigital ElectronicsVerilog+2

Education

ABES Engineering College

Bachelor of Technology - BTech

Jan 2017Jan 2021

Sobtis Public School Senior Secondary

Intermediate — Science

Mar 2015Mar 2016

Radha Madhav Public School

High School

Jan 2013Jan 2014

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