Aswini K P

Product Engineer

Bengaluru, Karnataka, India7 yrs 6 mos experience

Key Highlights

Expert in Static Timing Analysis and RTL Design.
Proven track record in multi-FPGA prototyping validation.
Achieved significant power reduction in physical design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in FPGA and physical design optimization.

Contact

Skills

Core Skills

Static Timing AnalysisRtl DesignPhysical DesignPower Optimization

Other Skills

Validation of designs for multi-FPGA Prototyping PlatformFull flow analysis from compile to FPGA programming file generationTiming analysisPlacement and routingPhysical Design FlowClock structure analysisTCL scriptingVerilogSynopsys ICC IIDigital ElectronicsMicrosoft OfficeMicrosoft WordMicrosoft ExcelMicrosoft PowerPointCadence Virtuoso

About

- Static Timing Analysis - Verilog/SystemVerilog for RTL design - HAPS-Protocompiler, XILINX Vivado, Synplify, Verdi, VCS - TCL & Shell scripting - Logic Synthesis Tools (Cadence & Synopsys DC) - ICC II Compiler

Experience

7 yrs 6 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

3 roles

Hw-assisted Verification | Staff Engineer

Feb 2024 – Present · 2 yrs 4 mos

Application Engineer Sr I, Systems Design Group

Jun 2022 – Mar 2024 · 1 yr 9 mos

Application Engineer II, Systems Design Group

May 2019 – Jun 2022 · 3 yrs 1 mo

Validation of designs for multi-FPGA Prototyping Platform.
Full flow analysis from compile to FPGA programming file generation including the timing, placement and routing.

Validation of designs for multi-FPGA Prototyping PlatformFull flow analysis from compile to FPGA programming file generationTiming analysisPlacement and routingStatic Timing AnalysisRTL Design

Intel corporation

Intern

Jan 2018 – Jun 2018 · 5 mos · Bangalore

Power Optimization in Physical Design Domain for Ethernet Project using 10nm
technology and achieved 50% reduction in clock power which inturn reduced the total dynamic power.
Power optimization is done by analyzing the clock structure and the distribution of the clock gating
cells, buffers, inverters & registers in the pre-cts & the post-cts database and by doing experiments
in ctmesh database.
Hands on training in Physical Design Flow (Netlist to GDSII) using Synopsys Tools (DC & ICC II
Compiler)
Have good knowledge in STA, TCL scripting.

Power OptimizationPhysical Design FlowClock structure analysisTCL scriptingPhysical Design