Pelageia Frolova — Software Engineer
PhD student in MIET, recently joined Synopsys team of engineers and really excited about my future in this company. Former worker of CAD development department in Russian Academy of Sciences. I took part in development of CAD tools for FPGA and SoC. For a few years my job was focused on the placement stage of design flow. Duting that time I developed architecture-aware delay model for timing-driven placement; few algorithms for initial placement. My PhD thesis is based on this work and it's focused on novel techniques for placement stage of IC design flow. Also I am interested in Machine Learning and Artificial Intellegence. I took some courses on Coursera and other educational platforms to improve my skills and learn something new.
Stackforce AI infers this person is a skilled engineer in the IC design and CAD development industry.
Location: Yerevan, Yerevan, Armenia
Experience: 5 yrs 4 mos
Skills
- Asic
- Physical Design
- Cad Development
- Ic Design
- Algorithm Development
- Timing Model Development
- Fpga Design
- Layout Design
Career Highlights
- PhD candidate focused on innovative IC design techniques.
- Experience in developing CAD tools for FPGA and SoC.
- Strong background in algorithm development and research.
Work Experience
Synopsys Inc
ASIC Physical Design Engineer II (1 yr 2 mos)
Alphachip
Senior Engineer (3 mos)
IPPM RAS (Russian Academy of Sciences)
Design Engineer (2 yrs 4 mos)
Russian Academy of Sciences (IPPM RAS)
Инженер-исследователь (1 yr 10 mos)
Стажёр-исследователь (9 mos)
Education
Аспирант at National Research University of Electronic Technology (MIET)
Магистр технических наук at National Research University of Electronic Technology (MIET)
Бакалавр технических наук at National Research University of Electronic Technology (MIET)