M M Kiran K — Software Engineer
Extensive experience in writing Test benches using System Verilog and UVM. Good experience in writing RTL models using Verilog HDL. Experience in using industry standard EDA tools for Simulation and Debug. Good understanding of test-plans for verifying correctness and performance of the design. Hands on experience of verification methodologies. Good understanding of ASIC design flow.
Stackforce AI infers this person is a highly skilled ASIC Design Engineer with expertise in digital design and verification.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 3 mos
Skills
- Rtl Design
- System Verilog
Career Highlights
- Expert in ASIC design and verification methodologies.
- Proficient in System Verilog and UVM for test bench development.
- Strong background in RTL design and EDA tools.
Work Experience
Synopsys Inc
ASIC Digital Design Staff Engineer (1 yr 4 mos)
ASIC Digital Design Sr Engineer (1 yr)
ASIC Digital Design Engineer - || (1 yr 5 mos)
Wipro
Project Engineer (1 yr 3 mos)
Chipsolve Technologies Private Ltd
ASIC Verification Engineer (1 yr 3 mos)
Maven Silicon
VLSI design and verification (1 yr 2 mos)
Education
Bachelor of Technology - BTech at Aditya College Of Engineering & Technology
