Kunal Sharma

Software Engineer

Sirsa, Haryana, India3 yrs 11 mos experience

Key Highlights

Specialized in RTL Design Verification for Ethernet PHY.
Expertise in Analog Design and Verification for LVDS I/O.
Proven track record in regression testing and collaboration.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in digital and analog verification.

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Skills

Core Skills

Rtl Design VerificationAnalog Design VerificationDigital Design Verification

Other Skills

SpecmanVerilogRTL DesignSynthesisCMOSAnalog Circuit DesignPVT corner analysisMonte Carlo simulationsDigital ElectronicsPythonPython (Programming Language)Digital IC DesignComputer ArchitectureAnalog CircuitsC (Programming Language)

About

Digital Design and Verification Engineer with 2+ years specializing in RTL Design Verification of IEEE 802.3 EthernetPHY and Analog Design & Verification of LVDS I/O. Expertise in HVL, Regression testing and Cross-functional collaboration ensuring first-pass silicon success

Experience

3 yrs 11 mos

Total Experience

Average Tenure

Current Experience

Nvidia

ASIC Engineer

May 2026 – Present · 1 mo · Bengaluru, Karnataka, India · Hybrid

Texas instruments

Digital Design Engineer

Dec 2024 – May 2026 · 1 yr 5 mos · Bengaluru · On-site

RTL Design & Synthesis of a Buffer to ease the verification of MIPI CPHY protocol in Palladium Emulator.
Verified 10+ Ethernet PHY features (WoL, Loopbacks, Low Power Modes) per IEEE 802.3 clauses.
Created test plans, modified the test environment, ran regression tests to ensure ongoing stability of the IP.

SpecmanVerilogRTL Design Verification

Synopsys inc

Analog Design Engineer

Jul 2023 – Dec 2024 · 1 yr 5 mos · Noida · Hybrid

Designed and verified LVDS Receiver for 5nm & 7nm nodes supporting 2 Gbps data rate with 1.8V analog/0.6V
digital supply per IEEE 1596.3.
Performed comprehensive Verification of Bandgap reference (BGR) circuit through PVT corner analysis, Monte Carlo simulations and aging verification.
Conducted schematic and post layout verification including transient, AC, DC and reliability analysis ensuring PPA optimization.

CMOSAnalog Circuit DesignAnalog Design Verification

Training and placement cell, nit kurukshetra

Placement Coordinator

May 2022 – May 2023 · 1 yr · Kurukshetra

Analog devices

Digital Design Engineer

Jan 2022 – Jun 2022 · 5 mos · Bengaluru · Hybrid

Verified digital subsystems by running regressions and debugged failures by analyzing test environment &
tracing back signals.
Developed Python automation script for post-processing simulation data across multiple bins, reducing analysis
time by 40%.
Ensured 100% code coverage through regression based testing.

VerilogDigital ElectronicsDigital Design Verification