MUTTANNA T PADASALAGI

Software Engineer

Bengaluru, Karnataka, India3 yrs 6 mos experience

Key Highlights

Expert in Analog Layout and VLSI design.
Proven track record in semiconductor projects.
Strong problem-solving and project management skills.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and Analog Circuit Design.

Contact

Skills

Core Skills

Very-large-scale Integration (vlsi)Analog LayoutAnalog Circuit Design

Other Skills

UCIEPERCGPIOCMOSElectronicsNetwork TheoryD2DEMIRParasitic cap/resMEMPHYPhysical VerificationElectrostatic Discharge (ESD)FinfetRibbon fetcustom compiler

Experience

3 yrs 6 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

2 roles

A&MS Layout Design Sr Engineer

Promoted

Jan 2025 – Present · 1 yr 5 mos

UCIEPERCVery-Large-Scale Integration (VLSI)Analog Layout

Analog Layout Engineer

Apr 2023 – Dec 2024 · 1 yr 8 mos

External/Contractor

GPIOCMOSAnalog LayoutVery-Large-Scale Integration (VLSI)

Elbrus labs

2 roles

Associate Layout Engineer

Promoted

Feb 2024 – Dec 2024 · 10 mos · Remote

GPIOCMOSAnalog LayoutVery-Large-Scale Integration (VLSI)

Junior Analog Layout Engineer

Apr 2023 – Feb 2024 · 10 mos · Remote

1.Worked on GPIO project 22nm
2.Placement of standard cells.
3.LVS and DRC verification
4.PERC checks,EMIR issues

GPIOCMOSAnalog LayoutVery-Large-Scale Integration (VLSI)

Siyacon technologies pvt ltd,

VLSI Anlog Layout Intern

Nov 2022 – Apr 2023 · 5 mos · Bengaluru, Karnataka, India

CMOSAnalog Circuit DesignVery-Large-Scale Integration (VLSI)

Education

KLE College of Engineering & Technology

Bachelor of Engineering - BE

Aug 2018 – Aug 2022

Gnyan Gangotri Independent Science PU College Jamakhandi

10+2 — PCMB

Jun 2016 – Jun 2018

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