Nov 2024 – Feb 2026 · 1 yr 3 mos · Bengaluru · On-site

• Full custom SRAM memory layout design for different technology nodes(Tsmc 3nm, Tsmc 6nm, Samsung 5nm ).
• Expertise in designing layout for many critical blocks of SRAM memory compilers and physical verifications DRC, LVS, DFM, EM/IR.
• Great understanding of designing critical block( like Sens amplifier,Predrv,Bist & Scan IOs etc)requiring concepts like Matching, Shielding.
• Have gone through all release phases
• includes LEF release, test chip release,
• full compiler release.
• Good experience in checking for feasibility and implementing of ECO in design. Followed by QA for compiler release.
• .Good Expertise in Instance LVS, Instance/Compiler DRC, EMIR..etc.Knowledge of challenges in recent technology nodes and it's impact on layout design.
• Good understanding for device fabrication and device physics.

Apr 2024 – Feb 2026 · 1 yr 10 mos

Feb 2022 – Apr 2024 · 2 yrs 2 mos

Apr 2022 – Nov 2024 · 2 yrs 7 mos · Noida

• Full custom SRAM memory layout design for different technology nodes(Intel 16nm, Samsung 8nm and Intel 18A).
• Expertise in designing layout for many blocks of SRAM memory compilers and physical verifications DRC, LVS, DFM, EM/IR.
• Great understanding of designing critical block requiring concepts like Matching, Shielding.
• Have gone through several release phases
• includes LEF release, test chip gds release,
• full compiler release.
• Good experience in checking for feasibility and implementing of ECO in design. Followed by QA for compiler release.
• Knowledge of challenges in recent technology nodes and it's impact on layout design.
• Good understanding for device fabrication and device physics.