Vishal Yadav

Software Engineer

Delhi, India3 yrs 10 mos experience

Key Highlights

Expert in Static Timing Analysis and Logic Synthesis.
Proven experience in physical design and ASIC solutions.
Strong background in circuit optimization and power analysis.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with expertise in ASIC design and timing analysis.

Contact

Skills

Core Skills

Static Timing AnalysisLogic SynthesisPhysical Design

Other Skills

Power AnalysisApplication-Specific Integrated Circuits (ASIC)Design Rule Checking (DRC)Layout Versus Schematic (LVS)Logic DesignCMOSLinuxEngineeringProject ManagementEnglishTrainingCommunicationStrategyAnalytical Skills

About

As a Senior Application Engineer at Synopsys Inc, I work on timing signoff, logic synthesis, physical design and application-specific integrated circuits (ASIC) solutions. My contributions include gate-level netlist debugging and employing power analysis techniques to support semiconductor design. With a Bachelor of Technology in Electronics and Communications Engineering from ABES Engineering College, my academic foundation complements my professional focus. My previous experience as a Physical Design/STA Engineer Trainee and Application Engineer has refined my skills in circuit optimization, timing analysis, and design flow setup, enabling me to contribute effectively to advanced electronic design solutions.

Experience

3 yrs 10 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

3 roles

Senior Application Engineer

Promoted

Feb 2024 – Present · 2 yrs 4 mos

Working extensively on AMD projects, performing the hierarchical analysis (Hyperscale).

Application Engineer 2

Jul 2023 – Feb 2024 · 7 mos

Application Engineer

Aug 2022 – Jul 2023 · 11 mos

Analysing and writing the SDC, run.tcl files, and gate level netlist . Creating test cases for reporducing the issues and debug for timing signoff.

Static Timing AnalysisLogic Synthesis

Vlsi expert private limited

Physical design/STA Engineer Trainee

Nov 2021 – Jul 2022 · 8 mos · Noida, Uttar Pradesh, India

Processor Design - (RTL2GDS) which includes
Design Flow: - setup for DC ICC and PT.
Complex Optimization in Synthesis:- SOC Level constraints with multi-cycle, asynchronous and multiple synchronous domain constraints.
MMMC setup for Automotive Specifications: - PVT corners analysis for the optimization of delay. Definition of Setup and Hold signoff criteria was setup.

Static Timing AnalysisPhysical design

Deki electronics ltd

Research And Development Engineer

Aug 2021 – Jul 2022 · 11 mos · Noida, Uttar Pradesh, India

Circuit Analysis and involve in the manufacturing of film capacitor. Finding exact value of lumped elements to have resonance. Suggesting equivalent capacitor on the basis of tan d, capacitive value, IR, power dissipation and application.