Carrie Marwein

Software Engineer

Noida, Uttar Pradesh, India3 yrs 4 mos experience

Key Highlights

Expert in SRAM architecture and memory design.
Hands-on experience with advanced technology nodes like 3nm and 4nm.
Proficient in multiple semiconductor design tools.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory architecture and characterization.

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Skills

Core Skills

Memory DesignSram Architecture

Other Skills

Synopsys customer compilerHspicetcq optimizationwrite marginbitcellanalysisreadassistsense amplifierShell ScriptingCMOSWorking MemoryArchitectural DesignxafsdbCommunicationfsm

About

I am an experienced Design and Characterization Engineer with a strong background in semiconductor design and analysis. My expertise spans standard cell characterization, memory design, and SRAM architecture. With hands-on experience at industry leaders like Qualcomm, Insemi Technology, and Synopsys, I have contributed to advanced technology nodes such as 3nm and 4nm, ensuring high-quality characterization across multiple PVT conditions and delivering optimized .lib models. Proficient in tools like Synopsys Custom Compiler, HSpice, Verdi, and StarRC, I have a solid foundation in scripting (Shell, Perl), RTL design (Verilog HDL), and operating in Linux/Windows environments. I have worked on complex SRAM design projects, stability analysis (SNM, RNM, DNM), and sense amplifier design, alongside performing PPA analysis, margin analysis, and memory instance characterization. I am passionate about semiconductor technology and continuously strive to expand my technical expertise while contributing to innovative design solutions.

Experience

3 yrs 4 mos

Total Experience

1 yr

Average Tenure

11 mos

Current Experience

Globalfoundries

Senior Design Engineer

Jul 2025 – Present · 11 mos · Bengaluru, Karnataka, India

Qualcomm

Engineer 1

Oct 2024 – May 2025 · 7 mos · Bengaluru, Karnataka, India · On-site

Insemi technology services pvt. ltd.

Associate Design Engineer

Mar 2024 – Jun 2025 · 1 yr 3 mos · Bengaluru, Karnataka, India

Synopsys inc

Memory Design Intern

Jun 2022 – Jul 2023 · 1 yr 1 mo · Noida, Uttar Pradesh, India

Memory design R&D team
Worked on SRAM register file & good knowledge in Memory compiler architecture
Hands-on experience on TSMC tech nodes 22nm & 40nm
Conducted instance characterization and debug cycles for access time. gain knowledge in 6-T SRAM read/write assist schemes.
Perform interpolation, deration, and instance evaluations using mdpro, handling a wide range of instances (small, big, wide, tall, mid). Identified worst-case instances through detailed analysis and implemented ECOs for improved access time and timing closure
Performed comprehensive QA checks (Data QA and FEQA), supported dummy compiler release processes, and contributed to new PDK releases. Developed a strong understanding of memory architecture and schematics using Maxwell tools.
Analyzed device characteristics, including read current, cell leakage, and MEMCELL parameters (SNM, WT, WM, ICELL, ILEAK) & Bitcell Analysis

Synopsys customer compilerHspiceMemory DesignSRAM Architecture