Ben Cohen

Co-Founder

Palos Verdes Peninsula, California, United States15 yrs 4 mos experience

Highly Stable

Key Highlights

Authored multiple influential books on SystemVerilog.
Contributed extensively to verification forums and publications.
Expertise in Functional Verification and SystemVerilog Assertions.

Stackforce AI infers this person is a seasoned expert in Semiconductors with a focus on design verification and SystemVerilog.

Contact

Skills

Core Skills

SystemverilogFunctional Verification

Other Skills

Computer ScienceVHDLVerilogASICRTL designModelSimFPGAEDAIntegrated Circuit DesignUVMOpen Verification MethodologyDebuggingMicroprocessorsSoCVLSI

About

https://www.perplexity.ai/search/write-an-about-ben-cohen-syste-V4sK72CnQRymaz0nAWynow Siemens Partner Design engineer and consultant. Author of several books and papers https://systemverilog.us/

Experience

15 yrs 4 mos

Total Experience

7 yrs 8 mos

Average Tenure

Current Experience

Self publisher

author

Jan 2009 – May 2009 · 4 mos

Since 1995 I wrote several books on VHDL, Verilog PSL, OVM, and SVA.
The SVA and PSL books weretranslated into Japanese

Computer Science

Vhdlcohen publishing

Contributor at the verificationacademy forums systemverilog

Apr 2000 – Present · 26 yrs 2 mos · Los Angeles, California, United States

http://www.systemverilog.us/ ben@systemverilog.us
SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
Links to papers and books https://docs.google.com/document/d/1W488Af-UiHJ9V6bHsmim4ge607JSfWCYXuSrz_lHNTM/edit?usp=sharing
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books:
Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
A Pragmatic Approach to VMM Adoption
http://SystemVerilog.us/vf/VMM/VMM_pdf_release070506.zip
http://SystemVerilog.us/vf/VMM/VMM_code_release_071806.tar
3) Papers:
Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
Reflections on Users’ Experiences with SVA, part 1
https://verificationacademy.com/verification-horizons/march-2022-volume-18-issue-1/reflections-on-users-experiences-with-systemverilog-assertions-sva
Reflections on Users’ Experiences with SVA, part 2
https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
https://verificationacademy.com/forums/coverage/sva-statistical-analysis-weighted-work-conserving-prioritized-round-robin-arbiter.
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/