Mar 1999 – Sep 2019 · 20 yrs 6 mos · Bangaon Area, India

• Professional Profile
•  20+ years of experience in various aspects of VLSI design such as Synthesis, Design for Test, Placement, Optimization, Clock Tree Synthesis, Routing, Static Timing Analysis (STA), Engineering Change Order (ECO), Formal Verification.
•  Responsible for multiple Regression Suite Validation and multiple feature testing of Fusion Compiler (FC), Design Compiler (DC), DFT Compiler (DFTC), Power Compiler, IC Compiler (ICC), IC Compiler II (ICCII), PrimeTime, TetraMAX and Formality.
•  Specialization in analyzing/debugging issues/failures.
•  Sound knowledge of Milkyway & NDM Data Model, LEF, DEF, Verilog, VHDL.
•  Strong track record of owning responsibilities and delivering high quality results with challenging schedule.
•  Strong track record of learning anything new either tool or feature very quickly and validate/test them at a very short time period.
•  Hands on experience and in-depth knowledge of full chip and block level ASIC design flow from synthesis to GDSII.
•  Expert in automating manual work and using various scripting languages on the fly to streamline/simplify repetitive tasks involving analysis/fixing issues/violations and generate/parse/summarize reports.
•  Very strong communication skills with peers, juniors and seniors.
•  Enjoy tough challenges, new learning opportunities and solving difficult problems.
• Specialties:
•  Tools: DC, DC NXT, DFT, IC Compiler, IC Compiler II, Prime time SI, Formality, StarRC, TetraMAX, IC Validator
•  Language/Scripts: TCL, Perl, Awk, sed, Make, Verilog, VHDL, LEF, DEF
•  Database: Milkyway, NDM