Vishal Manchanda

Product Engineer

Hyderabad, Telangana, India7 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Cadence Virtuoso and Calibre tools.
Strong background in analog layout design for semiconductors.
Proven teamwork and strategic planning skills.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog layout design.

Contact

Skills

Core Skills

Cadence Virtuoso Layout EditorCalibre

Other Skills

TCLPerlUnixICVStrategic PlanningPublic SpeakingTeamwork

About

Layout Engineer working in the semiconductors industry. Skilled in Cadence Virtuoso Layout Editor, Synopsys Custom Compiler, Teamwork and Strategic Planning. Strong engineering professional with a Bachelor of Technology focused in Electronics and Communications Engineering from JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA.

Experience

7 yrs 3 mos

Total Experience

3 yrs 7 mos

Average Tenure

4 yrs 4 mos

Current Experience

Synopsys inc

2 roles

Staff Layout Designer

Promoted

Jan 2025 – Present · 1 yr 5 mos

Senior Layout Designer

Jan 2022 – Dec 2024 · 2 yrs 11 mos

Invecas

3 roles

AMS Layout Design Engineer II

Feb 2021 – Jan 2022 · 11 mos

AMS Layout Design Engineer I

Feb 2020 – Jan 2021 · 11 mos

AMS Layout Design Trainee

Jan 2019 – Mar 2020 · 1 yr 2 mos

Veda iit

Analog Layout

Jul 2018 – Dec 2018 · 5 mos · Hyderabad, Telangana, India

Trained in shell languages such Linux and Unix and basic subjects like Network Analysis.
Training of Analog Layout Design started with the TSMC-28nm node in the Cadence Virtuoso.
Initially designed the logic gates (AND ,NAND,NOR,OR etc.) and learned to make the DRC and LVS clean layout using the Calibre tool.
Designed the more complex blocks like OP-AMP, learnt about the XL connectivity and concepts such as Matching, Latch-up, EM, cross-talk, Layout dependent effect, together with learning scripting languages SKILL, TCL, PERL.
At the end of training we did the layout of PLL circuit in the 22nm-FDSOI node of GF (Floorplan, Routing, Physical Verification).