P

Pravesh Bhandari

Software Engineer

Gyeonggi, South Korea10 yrs 7 mos experience

Key Highlights

  • Expert in Physical Verification and Design Rule Checking.
  • Proficient in multiple programming languages including Python and Perl.
  • Experience in ASIC Design and Full Custom Layout.
Stackforce AI infers this person is a VLSI Engineer specializing in Physical Verification and ASIC Design.

Contact

LinkedIn

Skills

Core Skills

Physical VerificationDesign Rule Checking (drc)Asic DesignDigital ElectronicsElectronics

Other Skills

Python (Programming Language)IC ValidatorTCLCalibrePerlAutomationScriptingBashSchematic Design - CombinationalVerilogFundamentals of electronic devicesDigitalXilinx ISEProteusShell Scripting

About

VLSI Engineer - Physical Verification Runset/Ruledeck developer Worked on Antenna, High Voltage, MPT and Metal Design Rules Runset Sanity and QA Runset and PV tool solutions to Samsung Development and QA flow improvement

Experience

10 yrs 7 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

4 roles

Staff Engineer

Feb 2025 – Present · 1 yr 4 mos

Python (Programming Language)Design Rule Checking (DRC)IC ValidatorPhysical VerificationTCLCalibre+3

Application Engineer

Promoted

Dec 2023 – Present · 2 yrs 6 mos

Design Rule Checking (DRC)IC ValidatorPhysical VerificationTCLPerlAutomation+1

Application Engineer

Jun 2020 – Dec 2023 · 3 yrs 6 mos

Design Rule Checking (DRC)IC ValidatorPhysical VerificationTCLBashAutomation+1

Technical Intern

Aug 2019 – Jun 2020 · 10 mos

Design Rule Checking (DRC)IC ValidatorPhysical VerificationTCLBashAutomation+1

Pine training academy

Trainee

May 2017 – May 2019 · 2 yrs · Ghaziabad, Uttar Pradesh, India

  • May 2017 to July 2018 : Trainee at PinE Training Academy @Electronics Hardware & Software System Design using Digital/Analog/RTL & Embedded C
  • July 2018 till date : Trainee at PinE Training Academy in ASIC Design and Full Custom Layout.
Schematic Design - CombinationalVerilogFundamentals of electronic devicesDigitalDesign Rule Checking (DRC)Digital Electronics+10

Inderprastha engineering college

Student

Aug 2015 – May 2019 · 3 yrs 9 mos · Uttar Pradesh, India

  • Studying under Electronics and Communication department.
Schematic Design - CombinationalCElectronicsFundamentals of electronic devicesDigitalMicrosoft Office+6

Education

IPEC

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2015 – Jan 2019

Kendriya Vidyalaya

10+2 — Science

Jan 2003 – Jan 2015

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