Shyam I. — Product Engineer

Semiconductor design engineer with 8+ years of experience across Physical Design, timing methodology, STA, and frontend-to-backend handoff flows. Experienced in RTL-to-GDS2 implementation and signoff across advanced technology nodes including Samsung 4nm/2nm, TSMC N2/N2P, and Intel 18AP, involving full-chip, test-chip, and mixed-signal IP implementation. Hands-on experience in floorplanning, multi-voltage power planning, CTS, routing, chip finish, EMIR analysis, physical verification, MCMM timing closure, ECO convergence, and full-chip integration activities including IO planning, bump/RDL routing, and seal-ring implementation. Strong expertise in advanced-node signoff flows including DRC/LVS closure, Formality verification, and Liberty timing/power model generation. Prior experience in timing methodology and frontend-to-backend handoff flows involving STA, synthesis enablement, timing model generation, and design quality validation across SoC and Graphics IP environments. Hands-on experience with PrimeTime, Fusion Compiler, StarRC, RedHawk_SC, and scripting using Tcl/Perl for improving design convergence and flow efficiency.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 8 mos