Vraj Patel — Software Engineer
Detail oriented IP Design Verification Engineer with 3+ years of experience in pre-silicon functional verification of complex ASIC IP blocks. Proven expertise in architecting robust SystemVerilog/UVM testbenches from scratch, implementing Coverage Driven Verification, and driving verification closure. Strong track record of identifying critical RTL bugs early in the design cycle using constrained random testing and comprehensive coverage analysis.
Stackforce AI infers this person is a skilled ASIC Verification Engineer with a focus on pre-silicon functional verification.
Location: Pune, Maharashtra, India
Experience: 3 yrs
Skills
- Functional Verification
- Systemverilog
Career Highlights
- 3+ years in ASIC IP design verification.
- Expert in architecting SystemVerilog/UVM testbenches.
- Proven track record in early bug identification.
Work Experience
Synopsys Inc
Sr ASIC Digital Design Engineer (1 yr 4 mos)
ASIC Digital Design Engr, I (1 yr 8 mos)
Intern - Technical Engineering (5 mos)
eInfochips (An Arrow Company)
Summer Intern (2 mos)
Education
Bachelor of Technology - BTech at Nirma University
Minor Specialization at Nirma University
