Ronak Nainiwal — Software Engineer

ASIC Digital Design Engineer with close to 4 years of experience at Synopsys, specializing in micro-architecture and RTL design of high-performance PCIe Transaction Layer datapaths. My work focuses on building timing-critical, protocol-accurate designs that operate under aggressive frequency and throughput targets. I have been involved in designing and optimizing PCIe Gen7 receiver datapaths at advanced technology nodes, including re-architecting critical logic to achieve stable 2 GHz timing closure at 3nm. I have worked on multi-TLP processing, unordered I/O handling, and multi-Virtual Channel (VC) capable datapaths, with a strong emphasis on throughput optimization, latency reduction, and robust backpressure handling. My role involves end-to-end ownership of RTL from micro-architecture definition to tape-out readiness, along with deep involvement in debugging complex RTL/testbench issues and ensuring coverage closure. Core strengths: • Micro-architecture and RTL design for complex datapaths • Timing closure at advanced nodes (3nm) • Performance optimization (throughput, latency, pipeline design) • Debugging and root-cause analysis of complex issues • Formal verification for corner-case validation

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in high-performance ASIC design and verification.

Location: Jaipur, Rajasthan, India

Experience: 3 yrs 11 mos