Madhuri Kadam

Software Engineer

Mumbai, Maharashtra, India18 yrs 4 mos experience

Highly StableAI Enabled

Key Highlights

12 years of academic expertise in VLSI and semiconductor fundamentals.
Developed advanced analog blocks for high-speed data transmission.
Ranked top in multiple national circuit design competitions.

Stackforce AI infers this person is a Semiconductor Engineer specializing in Mixed-Signal IC Design and Analog Circuit Development.

Contact

Skills

Core Skills

Mixed-signal Ic DesignAnalog Circuit DesignPerformance VerificationResearch And Development

Other Skills

Serializer with LVDS driverBandgap reference circuitAnalog Space Optimization (ASO.ai)Monte Carlo analysishigh-capacity variation analysisPrimeSim VCS mixed-signal simulationlow-noise LDOsDC-DC convertersanalog simulation toolshigh-speed dataCharge Pump Phase-Locked Loop (PLL)mixed-signal circuit simulationeSim (Ngveri)diagnosed technical issuesresolved technical issues

About

Analog & Mixed-Signal Engineer with hands-on experience in circuit design, simulation, and validation, complemented by 12 years of academic expertise in VLSI and semiconductor fundamentals. Demonstrated capability in designing key analog blocks, including bandgap reference, two-stage CMOS op-amp and serializer with LVDS driver across nodes (BCD1340HP, 28nm iPDK).

Experience

18 yrs 4 mos

Total Experience

4 yrs 10 mos

Average Tenure

3 yrs 4 mos

Current Experience

Synopsys inc

2 roles

Staff AMS Engineer

Promoted

Feb 2024 – Present · 2 yrs 4 mos · On-site

Developed Serializer with LVDS driver, enabling high-speed data transmission for high-speed IP (DDR5). Designed Bandgap reference circuit (BCD1340HP) to ensure stable voltage generation across process and temperature variations. Established Analog Space Optimization (ASO.ai) workflows for LDO design, improving design efficiency and optimization accuracy. Implemented advanced Monte Carlo and high-capacity variation analysis for SRAM yield sign-off, achieving 2x performance improvement, 50% reduction in PVM and maintained accuracy. Developed PrimeSim VCS mixed-signal simulation setup for PMIC design on BCD1340HP node, delivering 1.7x runtime improvement. Designed low-noise LDOs and DC-DC converters, ensuring stable operation across PVT corners. Evaluated and deployed next-generation analog simulation tools (PrimeSim SPICE/Pro, XA, Custom Compiler), driving ~10% improvement in product performance. Partnered with cross-functional teams and business stakeholders to resolve complex issues, gather requirements and enhance application performance. Provided technical leadership and mentorship, strengthening team capability while building and maintaining comprehensive documentation and knowledge repositories.

Serializer with LVDS driverBandgap reference circuitAnalog Space Optimization (ASO.ai)Monte Carlo analysishigh-capacity variation analysisPrimeSim VCS mixed-signal simulation+5

AMS Engineer Sr I

Jan 2023 – Jan 2024 · 1 yr · On-site

Fossee

Teaching Assistant

Jan 2022 – Jan 2023 · 1 yr · Mumbai, Maharashtra, India

Vlsi system design

Research Intern

Jun 2021 – Dec 2021 · 6 mos · Bangalore Urban, Karnataka, India

Indian institute of technology, bombay

Teaching Assistant

Jan 2021 – Jan 2023 · 2 yrs

Designed Charge Pump Phase-Locked Loop (PLL) in 130nm technology (Sky130), ensuring stable frequency synthesis and performance optimization. Built and validated analog and digital IPs using eSim (Ngveri) for mixed-signal circuit simulation, improving design accuracy and verification efficiency.

Charge Pump Phase-Locked Loop (PLL)mixed-signal circuit simulationeSim (Ngveri)Mixed-Signal IC Design

Shree l. r. tiwari college of engineering

Assistant Professor

Jul 2011 – Jan 2023 · 11 yrs 6 mos · Thane, Maharashtra, India

University of mumbai

Assistant Professor

Jan 2010 – Jan 2022 · 12 yrs

Ranked Top 7 out of 3,000+ participants nationwide in Circuit Simulation Marathon (eSim & Sky130) organized by IIT Bombay (FOSSEE) and VSD Corp. Awarded “Excellent” category (Top 65 of 2,000+ participants) in Mixed Signal Circuit Design Marathon (eSim) conducted by IIT Bombay, VSD and Redwood EDA. Secured Top 243 position among 2,500+ participants in Analog IC Design Hackathon organized by IIT Hyderabad, VSD and Synopsys.

K.c.college of engineering - india

Lecturer

Jan 2010 – Jul 2011 · 1 yr 6 mos · Thane, Maharashtra, India

Hcl infosystems ltd.

Research And Development Engineer

Sep 2008 – Jan 2009 · 4 mos · Mumbai, Maharashtra, India

Adtron technologies pvt. ltd.

Research And Development Engineer

Jan 2008 – Jan 2010 · 2 yrs

Diagnosed and resolved technical issues in educational electronic laboratory kits, including QPSK and BER systems, improving system reliability and minimizing downtime during lab sessions.

diagnosed technical issuesresolved technical issueseducational electronic laboratory kitsResearch and Development