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Yamini Gayathri T

Software Engineer

Bengaluru, Karnataka, India11 yrs 1 mo experience

Key Highlights

  • Experienced in Functional Verification and UVM methodologies.
  • Strong background in ASIC and SoC design.
  • Proven track record in verification engineering roles.
Stackforce AI infers this person is a Verification Engineer with expertise in ASIC and SoC design.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationUniversal Verification Methodology (uvm)

Other Skills

System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)RTL Verification

Experience

11 yrs 1 mo
Total Experience
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Average Tenure
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Current Experience

Ibm

Functional Verification Engineer

Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)Universal Verification Methodology (UVM)Functional VerificationRTL Verification

Synopsys inc

2 roles

ASIC Digital Design Staff Engineer

Promoted

Jan 2024 – Jun 2024 · 5 mos · Bangalore Urban, Karnataka, India

ASIC Digital Design Engr, II

Jan 2022 – Jan 2024 · 2 yrs · Bangalore Urban, Karnataka, India

Mirafra technologies

Verification Engineer II

Apr 2021 – Jan 2022 · 9 mos · Bangalore Urban, Karnataka, India

Maxvy technologies pvt ltd

Verification Engineer

Apr 2019 – Mar 2021 · 1 yr 11 mos · Bangalore Urban, Karnataka, India

Chipedge technologies pvt ltd

Verification Trainee

Aug 2018 – Jan 2019 · 5 mos · Bangalore Urban, Karnataka, India

Acs college of engineering

Assistant Professor

Dec 2014 – Jul 2018 · 3 yrs 7 mos · Bangalore Urban, Karnataka, India

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI Design

Jan 2010 – Jan 2012

Vellore Institute of Technology

Bachelor of Technology - BTech — Electronics and Instrumentation Engineering

Jan 2006 – Jan 2010

Shrishti Matric Higher Secondary School, Vellore

12th

Jan 2005 – Jan 2006

VVNKM CBSE School

10th

Jan 2003 – Jan 2004

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