Aishwary Dadheech — Software Engineer
● 10 years of experience in Physical Domain. ● Worked on 7nm,16nm,28nm timing closure, STA, Physical verification, IR drop/Power/EM Analysis, functional and timing ECOs, scripting etc. ● Working on Full Chip Flat/Hierarchical Timing Analysis. ● Worked as CAD team member for block level IR & EM flow development & Maintenance. ● Worked on Full Chip Flat/Hierarchical Extraction. ● Well equipped with ASIC Physical Design (P & R, Netlist to GDSII) Techniques, Flow Automation and Layout Verification. ● Experience in handling a team effectively. ● Ability to work simultaneously on multiple blocks/Tasks. ● Excellent interpersonal skills with abilities to meet deadlines & work under pressure. ● Good knowledge of scripting languages such as python, perl, tcl, & csh scripting.
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on ASIC Physical Design.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 10 mos
Skills
- Physical Design
- Static Timing Analysis
- Asic
Career Highlights
- 10 years of experience in Physical Domain.
- Expert in timing closure and physical verification.
- Strong scripting skills in Python, Perl, and TCL.
Work Experience
NVIDIA
Senior Physical Design Engineer (4 yrs 8 mos)
Juniper Networks
ASIC Physical Design Engineer (3 yrs)
eInfochips (An Arrow Company)
Technical Physical Design Lead (7 yrs 2 mos)
Education
Bachelor of Technology (B.Tech.) at Sir Padam pat Singhania University,Udaipur
