Ajay Kumar Dewangan

Software Engineer

Raipur, Chhattisgarh, India4 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in VLSI CAD and RTL Design.
  • Strong background in static timing analysis.
  • Proven problem-solving and communication skills.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in ASIC development.

Contact

LinkedIn

Skills

Core Skills

Vlsi CadRtl Design

Other Skills

Static Timing AnalysisLogic SynthesisLayout DesignCadence VirtuosoCadence Virtuoso Layout EditorELDOMemory DesignEngineeringEnglishResearchCommunicationProblem Solving

Experience

4 yrs 3 mos
Total Experience
2 yrs 1 mo
Average Tenure
3 yrs 11 mos
Current Experience

Synopsys inc

ASIC Digital Design Engr, II

Jul 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India

Static Timing AnalysisVLSI CADRTL DesignLogic SynthesisLayout DesignCadence Virtuoso+3

Ibm

Hardware Intern

Jan 2022 – Jun 2022 · 5 mos · Bengaluru, Karnataka, India

  • Hardware Intern at DFT Team

Indraprastha institute of information technology, delhi

3 roles

Teaching Assistant

Jun 2021 – Aug 2021 · 2 mos

  • Basic Electronics

Teaching Assistant

Jan 2021 – May 2021 · 4 mos

  • Integrated Electronics

Teaching Assistant

Sep 2020 – Dec 2020 · 3 mos

  • MTH-Real Analysis

Education

Indraprastha Institute of Information Technology, Delhi

M.Tech — VLSI & ES

Jan 2020 – Jan 2022

National Institute of Technology Raipur

B.Tech — Electronic and Communications Engineering Technology

Aug 2016 – Apr 2020

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