Akansha Suneria

Software Engineer

Bengaluru, Karnataka, India13 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 12 years of experience in hardware verification.
Expertise in PHY/SERDES IPs and Packet Processor IPs.
Proficient in Verilog, System Verilog, and UVM.

Stackforce AI infers this person is a Hardware Verification Engineer with expertise in semiconductor and IP verification.

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Skills

Core Skills

VerificationPacket Processor IpSoc DesignPower Aware VerificationFunctional VerificationMulti-protocol IpsTestbench DevelopmentMulti-protocol Design VerificationIp VerificationCode CoverageBlock Level Verification

Other Skills

SVUVMUPFSOCHBM protocolPCIe GEN4USBFormal verificationFunctional coverageSV assertionTest chip verificationATE environmentSublvdsSlvsDphy protocols

About

Hardware verification engineer with 12+ years of experience in front end functional verification. Expertise in verification of PHY/SERDES IPs (PCIe, USB), Packet Processor IPs (BTC,BLE,UWB). Skilled in Verilog, System Verilog, Specman, UVM, Formal verification tools.

Experience

13 yrs

Total Experience

2 yrs 7 mos

Average Tenure

4 yrs 4 mos

Current Experience

Qualcomm

Senior Lead Engineer

Jan 2022 – Present · 4 yrs 4 mos

Working on Packet Processor IP/SS verification using SV/UVM

SVUVMVerificationPacket Processor IP

Intel corporation

SoC Design Engineer

Jul 2019 – Dec 2021 · 2 yrs 5 mos · Bengaluru, Karnataka, India

Worked in Intel Server Group.
Verification of power aware flows with UPF in SS and SOC
Worked on Reset, clocks verification at SOC level
Memory Controller verification - HBM protocol

UPFSOCHBM protocolSoC DesignPower Aware Verification

Cadence design systems

3 roles

Lead Design Engineer

Promoted

Jul 2018 – Jun 2019 · 11 mos

o Functional verification of multi-protocol IPs (PCIe GEN4, USB, complex Serdes)
o Gate level simulation activity from setup, debug, timing violation analysis to closure
o Formal verification using Jasper apps such as CONN, FPV, UNR and CSR
o Expertise in code coverage, functional coverage and vplanner closure activities.
o Development of testchip environment and its full verification

PCIe GEN4USBFormal verificationCode coverageFunctional coverageFunctional Verification+1

Design Engineer II

Feb 2015 – Jun 2018 · 3 yrs 4 mos

o Testbench development from scratch for a Voltage monitor IP
o SV assertion based verification of design
o Test chip verification for multi-protocol design
o ATE environment development and post silicon support

SV assertionTest chip verificationATE environmentTestbench DevelopmentMulti-Protocol Design Verification

Design Consultant

Apr 2014 – Feb 2015 · 10 mos

o Verification of IP consisting of Sublvds, Slvs and Dphy protocols
o Code coverage closure activity
o Wreal simulations debug
o Test plan creation

SublvdsSlvsDphy protocolsWreal simulationsIP VerificationCode Coverage

Qlogic

Associate Engineer

Jul 2013 – Apr 2014 · 9 mos

o Worked on block level verification of PCIe design
o Automation of regression runs and reports

PCIe designAutomationBlock Level Verification

Texas instruments

Intern

Jul 2012 – Dec 2012 · 5 mos · Bangalore

o Research on low power circuit design techniques for microcontroller application at Kilby Labs.
o Analysed timing parameters and power values of conventional vrs low energy flops.
o Studied design parameters which affect power dissipation in CMOS design
o Worked at the research unit, Kilby Labs at Texas Instruments

Low power circuit designTiming parametersPower dissipation