Akshay Kinake

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expert in Full Chip timing signoff and SMC 3DIC STA.
  • Proficient in scripting languages: Perl, Python, Tcl.
  • Strong background in performance optimization for advanced SoC design.
Stackforce AI infers this person is a highly skilled ASIC Engineer specializing in timing and signoff for advanced semiconductor design.

Contact

Skills

Core Skills

Full Chip Timing SignoffSmc 3dic StaTiming ClosurePerformance Optimization

Other Skills

SMVADVFSConstraints DevelopmentManagementValidationPromotionDemotionCleanupPerlPythonTclCommunicationDevice PhysicsAdvanced SoC DesignClosure

About

Working as Senior ASIC Engineer in Timing & Signoff at Synopsys, I am responsible for rolling out new features with successful validations and resolving critical customer issues. I have experience working with Primetime, Constraints Consistency Checks (PTC/GCA), Tweaker ECO, PTECO, PrimeClocks, PrimeShield and PrimeClosure. Previously, I worked as a Hardware Intern at NVIDIA for one year in the timing and signoff team, where I was responsible for functional and test timing as well as performance optimization in advanced SoC design. I have experience in Full Chip timing signoff and SMC 3DIC STA, SMVA/DVFS, Constraints Development, Management, Validation, Promotion, Demotion, and Cleanup. I possess a good understanding of full chip, block-level SDCs, timing closure methodologies, and scripting languages such as Perl, Python, and Tcl.

Experience

3 yrs 11 mos
Total Experience
3 yrs 11 mos
Average Tenure
3 yrs 11 mos
Current Experience

Synopsys inc

3 roles

Staff Signoff Application Engineer

May 2026Present · 1 mo

Senior Signoff Application Engineer

Promoted

Feb 2024May 2026 · 2 yrs 3 mos

  • Experience in Full Chip & SMC 3DIC STA, SMVA/DVFS
  • Constraints Development, Management, Validation, Promotion, Demotion & Cleanup.
  • Good knowledge about Full chip, Block level SDCs & Timing closure methodologies and Scripting languages like Perl, Python and Tcl.
Full Chip timing signoffSMC 3DIC STASMVADVFSConstraints DevelopmentManagement+7

Signoff Application Engineer II

Jul 2022Feb 2024 · 1 yr 7 mos

CommunicationDevice Physics

Nvidia

ASIC Engineer Hardware Intern (Timing & Signoff)

Jul 2021Jun 2022 · 11 mos

  • Timing Closure and Performance Optimization In Advanced SoC Design
Timing ClosurePerformance OptimizationAdvanced SoC Design

Education

Sardar Vallabhbhai National Institute of Technology, Surat

Master of Technology in VLSI & Embedded Systems

Jan 2020Jan 2022

Walchand College of Engineering(A Govt. Aided Autonomous Institute),SANGLI-M.S

Bachelor's degree — Electronics Engineering

Jan 2014Jan 2018

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