Arunima G

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in advanced node physical design optimization.
Proficient in power integrity and chip reliability processes.
Strong background in RTL design and power analysis.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL design and power optimization.

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Skills

Core Skills

Rtl DesignPower Analysis

Other Skills

Analytical SkillsCadence VirtuosoSynopsys DCPPA OptimizationCadence InnovusEMIRCadence DSOPERLTCLC (Programming Language)VerilogProfessional ResponsibilitySocial ResponsibilityPersonal ResponsibilityAccepting Responsibility

About

To succeed in an environment of growth and excellence and to do job in which I can use my academic knowledge and which provides me self development opportunities.

Experience

4 yrs 11 mos

Total Experience

4 yrs 11 mos

Average Tenure

4 yrs 11 mos

Current Experience

Amd

3 roles

Senior Silicon Design Engineer

Promoted

Dec 2023 – Present · 2 yrs 5 mos

Contributed to advanced node physical design implementation and optimization across 7nm, 5nm, and 3nm technologies.
Executed EMIR (Electromigration and IR drop) integration and signoff processes to ensure robust power integrity and chip reliability.
Delivered comprehensive power analysis reports for both signoff and RTL feedback using PTPX and PowerArtist tools.
Designed and implemented a multi-voltage control unit for CPU core optimization, improving power efficiency and scalability.
Performed PPA (Power, Performance, Area) optimizations leveraging Cadence DSO tools to meet aggressive design goals.
Hands-on experience with Cadence Innovus for full-flow physical implementation.
Familiar with RTL architecture and flow, enabling close collaboration with front-end design teams for optimized handoff.

RTL DesignAnalytical SkillsCadence VirtuosoSynopsys DCPower AnalysisPPA Optimization