Manish Kumar Jain — Software Engineer

Total 16+ years of experience in the field of Physical Design of VLSI and have been part of 27+ successful full chip Tape outs. @ Qualcomm, my area of exposure has been Full chip Floorplan (all aspects), working with multiple teams (Architecture, Design/Integration, Package, Board, Cores etc) for an optimal SOC floorplan, Place and Route. Extensive work on IO limited designs. Gained knowledge of full design cycle. @Cadence, my work area was Hierarchical Partition domain and responsibility was to take care of Hierarchical partitioning, Feed through insertion and pin assignment related work. @Wipro Tecnologies, My main area of experience had been VLSI Physical Design Flow of multi-million gate full-chips. In the due course of project development related activities, I had complete exposure of full P&R flow and subsequently have gained experience over the project development lifecycle, client requirements and customer expectations. Area of Interest: VLSI – Complete Physical Design Flow (From Synthesis to Tapeout), Digital Logic Design Specialties: Full chip Floorplan (all the aspects), Communication Skills.

Stackforce AI infers this person is a VLSI Physical Design expert with extensive experience in semiconductor design and engineering.

Location: North Delhi, Delhi, India

Experience: 16 yrs 3 mos