Balakrishna Gone — Software Engineer

Experience in Synthesis and sta for 2nm, 3nm, 4nm, 5nm, 7nm and 8nm => Experience in Physical Design for 28nm,45nm and 65nm Technologies using Soc encounter and ICC => Worked on Physical Design flow stages like Floor planning, Place and Route, CTS, Timing Analysis. => Block level Timing Closure and Multi Voltage Design. Resolving various Block level Synth and PnR issues. => Expertise in Scripting Skills. => Highly adaptable to all kinds of environment. => Always on the look to improve skills and grow with the organization. => Good knowledge of CMOS concepts,latchup, IR drop, EM, digital design, cshell, perl. => Good knowledge in STA, setup, hold time analysis, Vlsi design flow from netlist to GDSII, => Hands on experience in Cadence first encounter, Synopsis IC compiler, PT, Dc compiler DC-NXT.

Stackforce AI infers this person is a VLSI design engineer with expertise in physical design and static timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 8 mos