Chirag Agarwal — Director of Engineering
* 21 years in the Semiconductor Industry doing RTL verification. Currently focused on formal verification. Has done RTL Coding, RTL Functional Verification, ABV (Assertion Based Verification). * Formal Verification, ABV experience with leading tools: JasperGold (Cadence), VCF (Synopsys), Hector (Synopsys), QuestaFormal (Mentor). * Rich experience of advanced functional coverage driven constraint based random verification methodologies while using System Verilog (OVM, VMM). Specialties: Formal Verification (JasperGold, VCF, QuestaFormal), Equivalence Checking (LEC) and Functional Verification (System Verilog)
Stackforce AI infers this person is a Formal Verification expert in the Semiconductor industry.
Location: Gurgaon, Haryana, India
Experience: 25 yrs 8 mos
Skills
- Formal Verification
- Functional Verification
Career Highlights
- 21 years in Semiconductor Industry
- Expert in Formal Verification methodologies
- Proficient with leading verification tools
Work Experience
NVIDIA
Formal Verification (4 yrs 7 mos)
Oski Technology, Inc.
Director Of Engineering (3 yrs 6 mos)
Oski Technology
Architect (10 yrs 3 mos)
Chip Design (Pvt) Ltd
Staff Engineer (4 yrs 1 mo)
Marvell Semiconductor India Pvt. Ltd.
Staff Engineer (1 yr 7 mos)
Agilent
MTS (2 yrs)
Centillium Communications
Verification Engineer (3 yrs)
Motorola Semiconductor
MTS (1 yr)
Education
at Indian Institute of Technology, Kanpur
