Deepak Kumar Mohapatra

Software Engineer

Bengaluru, Karnataka, India5 yrs 8 mos experience

Most Likely To Switch

Key Highlights

Experienced in Universal Verification Methodology and SystemVerilog.
Strong background in electronics and communication engineering.
Optimistic and adaptable professional seeking synergistic growth.

Stackforce AI infers this person is a Verification Engineer with expertise in semiconductor and electronics industries.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

Synopsys toolsUnix osMathematicsPython (Programming Language)EnglishBusiness Planning

About

I am modest and I remain optimistic through changes. I intend to build a career with a leading company that helps me nurture my experience and attain a responsible position according to my capabilities and learning abilities because I believe that the true goodness lies in synergistic growth towards prosperity.

Experience

5 yrs 8 mos

Total Experience

1 yr 10 mos

Average Tenure

2 yrs 1 mo

Current Experience

Qualcomm

Senior Engineer

May 2024 – Present · 2 yrs 1 mo · Bengaluru, Karnataka, India · On-site

Synopsys toolsUnix osUniversal Verification Methodology (UVM)SystemVerilogMathematicsPython (Programming Language)

Insemi technology services pvt. ltd.

2 roles

Verification Engineer

Promoted

May 2023 – May 2024 · 1 yr · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilog

Associate verification Engineer

Apr 2022 – Apr 2023 · 1 yr · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)SystemVerilog

Wipro limited

Project Engineer

Sep 2020 – Apr 2022 · 1 yr 7 mos · India

Universal Verification Methodology (UVM)SystemVerilog

Education

Silicon Institute of Technology (SIT), Bhubaneswar

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2016 – Jan 2020

UpendraNath College,Soro

Intermediate Science

Jan 2014 – Jan 2016

Stackforce found 100+ more professionals with Universal Verification Methodology (uvm) & Systemverilog

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