Divya Jamakhandi

Software Engineer

San Francisco, California, United States5 yrs 4 mos experience

Most Likely To Switch

Key Highlights

2+ years in Micro-architecture and RTL Design
Expertise in MMU IP for Qualcomm SOCs
Strong academic background with 4.0 GPA

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Microarchitecture and RTL Design.

Contact

Skills

Core Skills

MicroarchitectureVlsi

Other Skills

VerilogVery-Large-Scale Integration (VLSI)SystemVerilogCDCLintCore JavaC++Public SpeakingLeadershipC

About

2+ Years experience in Micro-architecture and RTL Design for MMU (Memory Management Unit) IP for Qualcomm SOCs across various tier chips. Worked on various MMU Blocks like Walker Logic, Cache control, interface protocols and Low Power Controllers. A Computer Architecture and VLSI enthusiast.

Experience

5 yrs 4 mos

Total Experience

1 yr 9 mos

Average Tenure

2 yrs

Current Experience

Apple

2 roles

GPU RTL Design Engineer

May 2024 – Present · 2 yrs · Austin, Texas, United States · Hybrid

GPU RTL Design Intern

May 2023 – Aug 2023 · 3 mos · Austin, Texas, United States · Hybrid

Worked on RTL design for various features for the Front End units of the Shader Core while meeting power, performance and area targets.
Worked on various design flows such as sequential equivalence checks, X-propagation checks and timing analysis.

College of natural sciences, the university of texas at austin

Graduate Teaching Assistant

Jan 2023 – May 2024 · 1 yr 4 mos · Austin, Texas, United States · On-site

Qualcomm

3 roles

Engineer

Promoted

Nov 2021 – Jul 2022 · 8 mos

SMMU IP RTL Design Engineer
Developed Micro Architecture and RTL from scratch for MMU blocks like Walker, Cache and interface protocols and delivered to Qualcomm SOCs across various tiers ranging from IoT to premium mobile applications.

VerilogVery-Large-Scale Integration (VLSI)SystemVerilogCDCLintMicroarchitecture+1

Associate Engineer

Jun 2020 – Nov 2021 · 1 yr 5 mos

SMMU IP RTL Design Engineer
Designed Power and Clock controllers to reduce the IP Leakage Power and support a Power Collapsible SMMU Island.
Worked on various post design RTL flows like Lint, CDC, STA and SOC debugs and efficiently handled multiple crucial ECOs by performing netlist modifications to implement equivalent RTL Logic for late bugs.

Engineering Intern

Jan 2020 – Jun 2020 · 5 mos

Designed micro-architecture and RTL for multiple PPA enhancement features on the base SMMU IP.

Indian institute of science (iisc)

Summer Research Intern

Jun 2019 – Aug 2019 · 2 mos · Bangalore

Implemented resource efficient 2D-Discrete Cosine Transform for feature extraction as a hardware accelerator and performed multiple layers of DCT aimed at extraction of features from Video frames on Zynq Ultrascale Board.

Imov motiontech

Embedded IOT Intern

Jun 2018 – Aug 2018 · 2 mos · IITM Research Park

Developed a Wheel Chair Monitoring system and worked on interfacing 3-Axis accelerometer and gyroscope with Arduino Development Board. Interfaced GSM Module, Real Time Clocks and External EEPROMS with the System.