Prashant Kashinkunti

Software Engineer

Bengaluru, Karnataka, India20 yrs 10 mos experience

Most Likely To Switch

Key Highlights

Over 6 years of experience in Physical Design.
Expertise in RTL development for major consumer devices.
Proven track record in timing closure and physical verification.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical and RTL design.

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Skills

Core Skills

Physical DesignTiming ClosureRtl Design

Other Skills

RTLGDSFloorplanningPower PlanningCTSSTAMicroarchitectureRTL DevelopmentSynthesisVLSIICHardware ArchitectureVHDLSoCPerl

About

IC Physical design Specialties: Expertise in complete physical design of ICs, Custom layout designs, Standard cell designs, Timing closure. Microarchitecture and RTL Design 6+yrs of Physical Design and 4+yrs of RTL design experience

Experience

20 yrs 10 mos

Total Experience

2 yrs 1 mo

Average Tenure

2 yrs 10 mos

Current Experience

Microsoft

Principal Engineer

Jul 2023 – Present · 2 yrs 10 mos · Bangalore

Amd

Principal Member Of Technical Staff

Apr 2022 – Jul 2023 · 1 yr 3 mos · Bengaluru, Karnataka, India

Qualcomm

Sr. Staff Engineer

Jul 2020 – Mar 2022 · 1 yr 8 mos · Bengaluru, Karnataka, India

Apple

ASIC design engineer

Oct 2018 – Jun 2020 · 1 yr 8 mos · Cupertino

Intel corporation

SoC Design Engineer

Feb 2016 – Oct 2018 · 2 yrs 8 mos · Santa Clara, California, United States

RTL - GDS flow. Full chip floorplanning, Power planning, CTS, Signoff. STA.
Synthesis and Physical Design

Microsoft corporation

2 roles

Hardware Engineer (Silicon Engineering Team)

Feb 2012 – Feb 2016 · 4 yrs · Mountain View, CA

Microarchitecture developement, RTL development, Synthesis and Timing closure.
RTL development for IPs that went into Xbox , Hololens and other Microsoft devices.

Hardware Design Intern (XBOX silicon development team)

May 2011 – Aug 2011 · 3 mos

RTL development for IPs that went into Xbox , Hololens and other Microsoft devices.

Carnegie mellon university

2 roles

Research Assistant

Aug 2011 – Dec 2011 · 4 mos

Through silicon Via configuration evaluation for 3D ICs inorder to reduce power density
Developed automation scripts for Physical design of memory sub systems

Graduate Student

Aug 2010 – Dec 2011 · 1 yr 4 mos

Major Courses
1. Digital IC design
2. Computer Architecture
3. Energy aware computing
4. System Verilog

Infineon technologies

Design Engineer

Feb 2005 – Jul 2010 · 5 yrs 5 mos

1. Worked on complete Physical design flow (Netlist - GDS) including floorplanning, power planning, CTS, Timing closure, Physical verification
2. Block level custom layout desing
3. Standard cell layout design