Harshitha Devadiga

CEO

Bengaluru, Karnataka, India10 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 7 years of experience in AMS layout engineering.
  • Expertise in advanced technology nodes from 3nm to 180nm.
  • Proficient in power management and serdes architecture layout design.
Stackforce AI infers this person is a semiconductor engineering expert with a focus on analog and mixed-signal layout design.

Contact

LinkedIn

Skills

Core Skills

Ams LayoutMask DesignAnalog LayoutSoftware Testing

Other Skills

CMOSVMware Virtualization TestingLayout DesignFloorplanningElectronic CircuitsCAD ToolsSemiconductorsFunctional TestingSystem TestingRegression TestingTest PlanningTest CasesStorage Area Network (SAN)Network-Attached Storage (NAS)Microsoft Excel

About

7 years of experience as AMS layout engineer. Dealt with 3nm ,4nm 5nm, 8nm, 45nm ,130nm and 180nm Technology nodes for Samsung and TSMC. Handled power management modules, transmitter receiver blocks and clock generators. well versed with serdes architecture layout design working for Qualcomm.

Experience

10 yrs 7 mos
Total Experience
3 yrs 6 mos
Average Tenure
4 yrs 9 mos
Current Experience

Qualcomm

2 roles

Lead layout engineer

Dec 2023 – Present · 2 yrs 5 mos

AMS layout engineer

Aug 2021 – Present · 4 yrs 9 mos

Mask DesignCMOSAMS layout

Mirafra technologies

Analog layout engineer

Dec 2017 – Jul 2021 · 3 yrs 7 mos

Mask DesignCMOSAnalog layout

Mphasis

Software Test Engineer

Jun 2015 – Sep 2017 · 2 yrs 3 mos · Bangalore

  • VMware Virtualization Testing
  • Software Testing
Software TestingVMware Virtualization Testing

Education

Dr M V Shetty Institute Of Technology

Bachelor of Engineering (B.Eng.) — Electronics and Communications Engineering

Jan 2011 – Jan 2015

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