Trivikram D.

Software Engineer

Bengaluru, Karnataka, India7 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in advanced semiconductor process technologies.
  • Proven track record in memory design and development.
  • Strong collaboration skills with circuit design teams.
Stackforce AI infers this person is a semiconductor engineering expert with a focus on memory design and physical verification.

Contact

Skills

Core Skills

Memory Design & DevelopmentPhysical Design

Other Skills

TeamworkLayout Versus Schematic (LVS)SRAMSynopsys IC CompilerFloorplanningcustom layout designDesign Rule Checking (DRC)Mask DesignIC LayoutLayout DesignAnalog LayoutSignalLayout ToolsLayout VerificationDesign Engineering

About

● Professional Summary Experienced semiconductor engineer with hands-on expertise across advanced process technologies and a deep understanding of memory design, physical verification, and layout optimization. Proven track record of delivering high-performance solutions for complex projects involving leading-edge nodes and device technologies. Adept at collaborating with circuit design teams and utilizing custom automation to streamline workflows. *Core Competencies* ● Process Technology Expertise: - Extensive experience with advanced technology nodes: N2/P, N3/E/P, N4P, N4LLP, N5, N16FF+, 22nm, 28nm, 40nm, and 45nm - Hands-on knowledge of major foundries: TSMC, GlobalFoundries (GF), and Samsung ● Memory Design & Development: - Successfully completed 65+ memory compilers across 11+ projects, including 4 test chips - Specialized in the design and implementation of SRAM and custom SRAMs for xPUs (e.g., CPUs, GPUs, NPUs) ● Device Technologies: - Expertise in cutting-edge semiconductor devices including Nano sheet, GAAFET, FinFET, FDSOI, and planar devices ● Physical Verification & Tools: - Proficient in critical verification tasks: DRC, LVS, VERC, DFM, LPE, ERC, PERC, Star RC and EMIR - Extensive experience with industry-standard tools: Calibre, ICV, Assura, LayPro, XARA and Totem ● Layout Design & Optimization: - Expertise in power/ground structure design, block placement, and floor planning - Mitigated issues such as latch-up prevention and signal cap matching - Addressed complex layout challenges, including high/low-density areas, antenna violations, metal density errors, and poly jumper corrections ● Collaboration & Problem Solving: - Engaged in continuous cross-functional collaboration with circuit design engineers to resolve design challenges and integrate required changes efficiently ● Automation & Workflow Optimization: - Developed and implemented custom BindKeys and scripts to enhance productivity and streamline workflows

Experience

7 yrs 11 mos
Total Experience
2 yrs 7 mos
Average Tenure
3 yrs 11 mos
Current Experience

Mediatek

2 roles

Senior Engineer in Computing and Artifical Intelligence III

Promoted

Jun 2022Present · 3 yrs 11 mos

  • Complete handing of xPU’S SRAM Design development.
TeamworkPhysical DesignMemory Design & Development

Physical Design Engineer

Nov 2020Jun 2022 · 1 yr 7 mos

TeamworkPhysical Design

Mirafra technologies

Layout Engineer II

Nov 2020Jun 2022 · 1 yr 7 mos · Bengaluru, Karnataka, India

TeamworkPhysical Design

Synopsys inc

Memory Layout Engineer

Oct 2019Nov 2020 · 1 yr 1 mo · Hyderabad, Telangana, India

TeamworkPhysical Design

Risetime semiconductors

2 roles

Layout Engineer

Dec 2018Nov 2020 · 1 yr 11 mos · Hyderabad, Telangana, India

TeamworkPhysical Design

Trainee

May 2018Nov 2018 · 6 mos · Hyderabad, Telangana, India

Physical DesignLayout Versus Schematic (LVS)

Education

BVC ENGINEERING COLLEGE - ODALAREVU (BVCE)

Bachelor’s Degree — Electronic and Communications Engineering

Jan 2013Jan 2019

Vidyanidhi Junior College

High School — M.P.C

Jan 2011Jan 2013

Sree Vidyavan The Concept School

High School — SSC

Jan 2008Jan 2011

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