prasanna nalawar

Operations Associate

Bengaluru, Karnataka, India19 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in SRAM memory compiler design and layout.
  • Proficient in Cadence tools for semiconductor design.
  • Strong background in VLSI and CMOS technologies.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SRAM and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

SramLayout Design

Other Skills

CadenceVLSIMask DesignCMOSPerl

Experience

19 yrs 10 mos
Total Experience
5 yrs 8 mos
Average Tenure
5 yrs 6 mos
Current Experience

Synopsys inc

3 roles

Sr. Manager

Promoted

Feb 2023 – Present · 3 yrs 3 mos

Team Manager

Nov 2020 – Feb 2023 · 2 yrs 3 mos

Manager

Sep 2014 – Mar 2019 · 4 yrs 6 mos · Bangalore

  • Responsible for developing SRAM memory compilers in 10nm technology.

Smic

Member Of Technical Staff

Mar 2019 – Nov 2020 · 1 yr 8 mos · Shanghai, China

Amd

Senior Design Engineer @ AMD India Pvt Ltd

May 2011 – Feb 2023 · 11 yrs 9 mos · Bangalore

  • 1. Responsible for high performance SRAM Memory Compiler Layout design in 20nm technology
  • 2. More than 2.5 years of experience in developing memory compiler layouts in both GF & TSMC.
  • 3. Good knowledge on latest layout trends/complications/challenges in 20nm technology
  • 4. Good knowledge and fast debugging of complicated DRCs in 20nm and also higher technologies
  • 5. Worked on high performance and high density memory compiler
  • 6. Experience on memory compiler development flow
  • 7. Experience on Memory compiler design methods/flows
SRAMLayout DesignCadenceVLSIMask DesignCMOS+1

Karmic

2 roles

Memory Layout Engineer

Promoted

Jul 2006 – May 2011 · 4 yrs 10 mos

  • 4 years of experience in memory esp SRAM layouts with Cadence Virtuso Tool.
  • Good layout experience on all types of SRAM achitectures.
  • Knowledge on Layout issues.
  • Knowledge on Skill and Perl languauges for automation.
  • Moderate knowledge on CMOS process fabrication.
  • Knowledge on differennt SRAM blocks like Bitcell, Sense Amp, predecoder etc..
SRAMLayout DesignCadence

Member of Tech Staff

Jul 2006 – May 2011 · 4 yrs 10 mos

CadenceCMOSPerlLayout Design

Education

B.L.D.E.As

Bachelor of Engineering (BE)

Jan 2002 – Jan 2006

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