Jay Panwar

Technical Recruiter

India3 yrs 8 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expertise in FPGA and high-performance computing.
Strong background in AI and machine learning.
Proficient in C++ and embedded software development.

Stackforce AI infers this person is a Technical Recruiter with a strong background in High-Performance Computing and AI.

Contact

Skills

Core Skills

Technology RecruitmentHuman Resources (hr)C++Field-programmable Gate Arrays (fpga)Embedded SoftwareArtificial Intelligence (ai)Machine Learning

Other Skills

Time ManagementTalent ManagementAttention to DetailCandidate AssessmentTalent SourcingApplicant Tracking SystemsInterviewingLow Level ProgrammingCode DesignLinuxAlgorithm DesignFPGAProgramming ConceptsDefining RequirementsAlgorithms

About

No two days are the same — each one is a new lesson in the game of life.

Experience

3 yrs 8 mos

Total Experience

1 yr 8 mos

Average Tenure

2 yrs 1 mo

Current Experience

Dexian

Technical Recruiter

May 2024 – Present · 2 yrs 1 mo · San Diego, CA · Remote

Field-Programmable Gate Arrays (FPGA)Time ManagementTalent ManagementTechnology RecruitmentHuman Resources (HR)Attention to Detail+4

Amd

Contract Software Engineer

Aug 2022 – Feb 2024 · 1 yr 6 mos · Hyderabad, Telangana, India · On-site

Developed a high-performance solution for solving linear systems of equations (AX = B) using QR Decomposition, targeting 512×256 matrices. Implemented on Vitis AI Engine architecture (Versal VCK190 FPGA board) using C++, achieving an impressive throughput of 10,000 matrices per second. Leveraged advanced linear algebra techniques optimized for FPGA-based acceleration.
Integrated AI Engine kernel development and applied vectorization techniques for maximum data-level parallelism.
Implemented performance-critical C++ code, optimized for throughput and low-latency performance in high-performance computing systems.
Utilized vectorization and High-Level Synthesis (HLS) to accelerate compute-intensive paths.
Implemented various DSP functions such as large point FFT’s (1 million & 64 k), FIR filter and General Matrix Multiplier on Vitis AI Engine in C++, Simulink Model Composer, and MATLAB.
Used template metaprogramming techniques to build generic, reusable code components for signal processing and matrix operations.
Designed and deployed custom AI Engine kernels for efficient parallel processing.
Obtained a good understanding of working with FPGA boards by creating, testing, and deploying codes on Xilinx FPGA boards such as Versal AI Core series VCK190.
Hands-on experience with AI Engine architecture and hardware-software co-design.
Acquired expertise in systems design and interactions with low-level hardware. Gained practical experience in HLS-driven development workflows for hardware-accelerated computation.

Low Level ProgrammingCode DesignC++LinuxAlgorithm DesignField-Programmable Gate Arrays (FPGA)

Innovation communications systems

Software Engineer

Jul 2022 – Feb 2024 · 1 yr 7 mos · Hyderabad, Telangana, India · On-site

Worked in developing, debugging, and maintaining reliable and clean code in object-oriented languages (C/C++).
Obtained a good understanding of working with FPGA boards by creating, testing, and deploying codes on Xilinx FPGA boards such as Versal AI Core series VCK190.
Acquired expertise in systems design and interactions with low-level hardware.
Gained experience with software development processes and version control tools (GitHub).

Programming ConceptsDefining RequirementsAlgorithmsMATLABC++Computer Architecture+2