Jitendra Puri — CEO

- Expertise in ASIC/FPGA Design and Verification - Design and Verification IP - Motherboard and Add-on card Design - Engineering Management - Software Engineering (including SEI-SMM Level 5 & ISO processes) - Technical Paper Presentations/Publications • MIPI Verification Made Easy @ MIPI conference, Osaka, Japan 2011 • Common Pitfalls in MIPI Designs @ MIPI conference, Osaka, Japan 2011 • Common Pitfalls in Ethernet Designs @ Ethernet Technology Summit, Santa Clara, USA 2011 • Next Generation Verification IPs @ Design & Reuse, IP SoC conference B'lore & Hsinchu 2010 • Common Pitfalls in SuperSpeed USB Designs @ DATE-10 conference, Dresden, Germany 2010 • Challenges in PCIe 3.0 Designs: Failure Teaches Success @ PCI-SIG conference, USA 2009 • “Citius, Altius, Fortius” Three Steps towards PCIe 2.0 Success @ PCI-SIG conference, USA 2008 • Common Pitfalls in PCIe 2.0 Migration @ PCI-SIG conference, USA 2007 • Integrating Verilog Bus Functional Models in VMM Environment @ SNUG, Taiwan 2007 • The dirty dozen in PCI Express designs @ EDA Tech Forum, 2006 • Techniques for Efficient Verification of PCIe to PCI Bridge @ PCI-SIG conference, USA 2006 • Common Pitfalls in PCIe design-2 @ PCI-SIG conference, London 2006 • Assertion Based Checkers for Serial Protocols: Special Considerations @ SNUG, San Jose 2006 • Common Pitfalls in PCIe design-1 @ PCI-SIG conference, USA 2005 • Building RVM Environment Above the Existing Legacy Verification Environment @ SNUG, Boston 2005 • PLIs In Verification Environment @ SNUG, San Jose 2002

Stackforce AI infers this person is a leader in ASIC and FPGA design within the semiconductor industry.

Location: West Delhi, Delhi, India

Experience: 31 yrs 11 mos