Kailash Kumar — Associate Partner
Experience from transistor level designing of simple IOLIBs conforming to JEDEC standard, to high voltage IOs,I2C(Master/Salve)/I3C,SILMBUS,SPI, SPMI,SDMMC,Slew Rate control(SRC),Tolerant and Fail Safe IO Buffer Design, etc, Full accountability from spec to silicon.. Wide range experience in technology (like B9MW,BCD,IMGING, CMOS 180nm to 28nm both in bulk and FDSOI, NVM.. etc) Design supporting higher voltages than device rating like designing 3.3V or 5.5V tolerant IO with 1.8V device. Low leakage Schmitt trigger Design when PAD voltage is less than supply voltage. Differential Schmitt trigger. Core-off and IO-Off Supply Detector Circuit Design. Power Sequence Free Mult-Supply and Multi-Drive I/O Buffer Circuit Design. Pad/Bus Keeper Circuit Design. IO Testchip schematic design. Circuit reliability and Aging.
Stackforce AI infers this person is a semiconductor design expert with a focus on VLSI and IO circuit technologies.
Location: Noida, Uttar Pradesh, India
Experience: 16 yrs 5 mos
Skills
- Io Circuit Design
- Silicon Qualification
Career Highlights
- Expert in IO circuit design and silicon qualification.
- Extensive experience in VLSI and semiconductor technologies.
- Proven track record in mentoring and technical leadership.
Work Experience
Synopsys Inc
Senior Manager (1 yr 4 mos)
Manager (2 yrs 8 mos)
Senior Design Engineer 2 (1 yr 5 mos)
STMicroelectronics
Staff Engineer (2 yrs 3 mos)
Technical leader (2 yrs 11 mos)
Senior design engineer (2 yrs 11 mos)
Design Engineer (2 yrs 11 mos)
Education
Bachelor’s Degree at BIT Mesra Student-Industry Relations Cell
at St. Robert's High School, Hazaribag
