kamal jyoti pathak — CEO

presently working as senior sta engineer in Qualcomm, Worked as senior physical Design engineer in sondrel (UK based company) earlier Research Scholar and senior asic lab engineer (physical design) from IIT-BHU with a demonstrated history of working in the education management industry. Skilled in Verilog, VHDL and tools of xilinx,mentor,synopsys,cadence. working for ASIC tapeout for govt project. Good at TCL Scripting. Have in depth knowledge of entire physical design process from floorplan till GDS generation Good at Block level physical design & Block level timing closure. Understanding of deep sub-micron design problems and solutions. Good at Congestion free Floor-planning with High Macro Count. Have ability to resolve congestion and timing issues at every stage of PnR flow. Good at CTS- Skew Minimization. Indepth knowledge of Digital design and CMOS Technology. Good at EM/IR analysis, Signal Integrity/X-Talk analysis. Good at DFM(Antenna, Redundant Via & Metal Density) & Physical Verification (DRC/LVS) and Low Power Design Techniques . Timing analysis with SI and OCV. Timing analysis with Clock Domain Crossing. Good knowledge of UNIX commands and GVIM editor. started VLSIFaB for helping freshers struggling to get enter into VLSI domain. https://www.youtube.com/channel/UC5oX3fnHimLVEOMygSxAjYw

Stackforce AI infers this person is a VLSI expert with a focus on ASIC design and physical verification.

Location: Varanasi, Uttar Pradesh, India

Experience: 10 yrs 5 mos