lenin yadav

Director of Engineering

Hyderabad, Telangana, India15 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI and Timing Closure.
  • Proficient in multiple PD tools and scripting languages.
  • Leadership experience in SOC implementation and IR-EM.
Stackforce AI infers this person is a VLSI and Physical Design expert with extensive experience in low-power SOC implementations.

Contact

Skills

Core Skills

VlsiTiming ClosureSoc ImplementationPhysical DesignIr-em

Other Skills

Static Timing AnalysisIR-EM and Power AnalysisFull-Chip BudgetingTCLPerlIntegrated Circuit DesignVerilogSoCASIC

About

Block level PnR, Block & FullChip Timing closure and IR/EM for low-power designs. Specialties: Substantial knowledge in several PD tools(encounter, icc, pt, sierra pinnacle, redhawk). good commanding in scripting(perl, tcl, c-shell, awk & sed)

Experience

15 yrs 10 mos
Total Experience
5 yrs 6 mos
Average Tenure
4 yrs 9 mos
Current Experience

Qualcomm

Senior Staff Manager

Sep 2021Present · 4 yrs 9 mos

VLSITiming ClosurePhysical DesignStatic Timing AnalysisIR-EM and Power Analysis

Amd

3 roles

SMTS

Jul 2017Sep 2021 · 4 yrs 2 mos

  • SOC-Impl Ip & IR-EM Lead
SOC ImplementationIR-EM

MTS

Promoted

Jul 2014Jun 2017 · 2 yrs 11 mos

  • Physical Design Ip Arch Lead and IR-EM Lead.
Physical DesignIR-EM

Sr. Physical Design Engineer

Apr 2011Jun 2014 · 3 yrs 2 mos

  • Tile Lead/Owner, worked Full-Chip budgeting and IR-EM.
Full-Chip BudgetingIR-EM

Soctronics

Sr. Engineer

Aug 2007Mar 2011 · 3 yrs 7 mos · Greater Hyderabad Area

  • joined as Project trainee and worked for AMD through Scotronics

Princton college of engg

Asst. Prof

Jul 2005May 2006 · 10 mos · Hyderabad

  • thought digital design and Vlsi

Education

Jawaharlal Nehru Technological University

M.S — VLSI

Jan 2006Jan 2008

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