Sai Charan Elluru

Software Engineer

Hyderabad, Telangana, India9 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in Physical Design and Static Timing Analysis.
Hands-on experience with advanced TSMC technologies.
Proven track record of successful tapeouts.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Timing Analysis.

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Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

signoffPNRDesign Rule Checking (DRC)erimPDSTAPVTIMINGEDA TOOLSCadence/Synopsys ToolsUNIXTCLLogic SynthesisDigital ElectronicsVery-Large-Scale Integration (VLSI)

About

Skills : PD, PNR, STA, PV, TIMING, EDA TOOLS, Cadence/Synopsys Tools, UNIX, TCL - Worked for 4 tapeouts as physical design Engineer. - Good knowledge and understanding of RTL-GDSII flow. - Hands-on experience in floorplanning, Place and Route (P&R) , Physical verification, EM, IR fixes, Static Timing Analysis (STA) and Timing Closure. - Experience in cadence, Synopsys design environment & calibre by Mentor Graphics. - Good scripting knowledge in TCL. - Worked on 3nm, 4nm, 5nm, 6nm, 7nm, 28nm technologies of TSMC.

Experience

9 yrs 9 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 6 mos

Current Experience

Synopsys inc

Staff Engineer

Dec 2022 – Present · 3 yrs 6 mos · Hyderabad, Telangana, India

working as staff engineer on Intel high end cpu cores from rtl to gds

signoffPNRDesign Rule Checking (DRC)erimPhysical DesignStatic Timing Analysis

Amd

Senior Silicon design engineer

May 2019 – Dec 2022 · 3 yrs 7 mos · Hyderabad

worked as sr physical design engineer on 4 ip tapeouts from rtl to gds which includes all low power designs and also worked on chip level secondary violations cleanup.

PNRPhysical Design