Mar 2013 – Oct 2014 · 1 yr 7 mos · Noida

• Memory Models : ST MICROELECTRONICS
• SPREG is a configurable memory model
• Developed Verification Environment in SV using UVM for Single port Memory Models.
• Developed Verification Components Agents, Monitors and Driver using SV- UVM methodology
• Tools Used : VCS (Synopsys) , Incisive (Cadnce), QuestaSim ( Mentor Graphics)

Jun 2012 – Nov 2012 · 5 mos · New Delhi Area, India

• AMBA AXI4 Stream, a bus-based High-Speed Communication Interface and an interconnect protocol optimized for high bandwidth and reliable packet transfer.
• Test Plan, Directed and Random Test Sequences, Functional Coverage using SV-UVM

Dec 2010 – May 2012 · 1 yr 5 mos · New Delhi Area, India

• AMBA AXI: Test plan and Test sequences for new features using the SV-OVM methodology
• Tools Used: VCS, DVE

Mar 2010 – Dec 2010 · 9 mos · Noida Area, India

• Developed Slave Component of AMBA AHB Slave Interface in Verilog.
• Tools Used: QuestaSim (Mentor Graphics)