Manjunathagowda G C — Software Engineer
Good Experience in Physical Design (RTL to GDS II Implementation/Methodology) Technology Node: 18A/20A/3/7/10/14/16/28/40 nm Areas of Interest: Physical Design, Physical Verification, STA, EM/IR Analysis, Synthesis, LEC, VCLP. Scripting in Perl and Tcl. Tools Used: • Physical Implementation : Fusion Compiler, ICC2, ICC, Innovus, Atoptech’s Aprisa, • Timing analysis : Prime Time, Tempus. • LEC: Conformal. • Physical Verification: Calibre. • Synthesis: Design Compiler, Genus. • ECO: PT-ECO, Tempus-ECO, Dorado/Tweaker MTech in VLSI Design and ES.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and verification.
Location: Bengaluru, Karnataka, India
Experience: 15 yrs 1 mo
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expertise in RTL to GDS II physical design methodology.
- Proficient in static timing analysis and physical verification.
- Strong background in VLSI design across multiple technology nodes.
Work Experience
Intel Corporation
Physical Design Engineer (9 yrs 6 mos)
Qualcomm
Senior Physical Design Engineer (1 yr 6 mos)
Broadcom
Staff Engineer, IC Design (3 yrs 2 mos)
Honeywell Technical Solutions Lab
Physical Design Intern (11 mos)
Education
Master of Technology - MTech at Dr.AIT, Bengaluru. VTU
BE at BTL Institute of Technology, Bengaluru. VTU
PUC at Nutana PU Science College, Davangere.
