Meghana V

Software Engineer

Bengaluru, Karnataka, India6 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

5.5 years of experience in VLSI industry.
Expertise in EDA tools for various technological nodes.
Strong background in Static Timing Analysis and Physical Design.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Static Timing Analysis and Physical Design.

Contact

Skills

Core Skills

Static Timing AnalysisTiming ClosurePhysical Design

Other Skills

Synopsys PrimetimeCross Talk AnalysisPNR FlowIntel CaliberTiming ReportsPrime Time ToolTCLUNIXCode Quality ChecksNoise AnalysisPNR ProjectsSanity ChecksDesign ImportFloor PlanningPower Planning

About

I have completed Masters in Digital Electronics (M.Tech) with CGPA of 8.1 from S.V University, Tirupati. I have 5.5 years of relevant experience in VLSI industry and I'm currently working for Tech Mahindra Pvt Ltd. I have hands on experience in EDA tools like Cadence Innovus, Genus, Virtuoso, Tempus and Synopsys Prime Time and worked on 7nm, 28 nm, and 45nm nodes. I currently support Prime time tool for STA team and play key role in Pre-production Testing, Code Quality Checks and Timing fixtures. I have good knowledge in UNIX, verilog and Tcl scripting. I also worked on Synthesis and PNR projects and have good experience in Floor planning, Power planning, Trail Route, Congestion Analysis, RC extraction, Timing Analysis, Clock Tree Synthesis, Detail Routing in both top level and block level designs. Possess basic knowledge in Layout designing and have worked on standard cell designing. The areas of projects which I've worked on is mostly in Place and Route Logical Synthesis, RTL to GDS , STA and Noise Analysis. Apart from this my academic project during my masters was on Digital Image processing. It was conversion of two dimensional images in different angles into single 3D image using Speed Up Robust Feature (SURF) technique.

Experience

6 yrs 8 mos

Total Experience

1 yr 8 mos

Average Tenure

4 yrs 4 mos

Current Experience

Mediatek

2 roles

Staff Engineer

Promoted

Jul 2025 – Present · 10 mos · Bengaluru, Karnataka, India

Senior Engineer

Jan 2022 – Jul 2025 · 3 yrs 6 mos · Bengaluru, Karnataka, India

Static Timing AnalysisSynopsys Primetime

Tech mahindra

Associate Engineer

Apr 2021 – Dec 2021 · 8 mos · Bangalore Urban, Karnataka, India

Worked On full Chip Timing Closure upon 10 nm technological node for Intel Client. Hands on experience in cross talk analysis and fixing. Worked on PNR flow. Have good expertise in running Intel Caliber and providing fixes.
Generating and debugging timing reports and providing fixes for setup and hold outliers.

Timing ClosureCross Talk AnalysisPNR FlowIntel CaliberTiming Reports

Synopsys inc

Technical Engineer( STA )

Feb 2020 – Feb 2021 · 1 yr · Bangalore

Suppored Prime Time tool . Worked on converting customer designs for enhancements, performing code quality checks, stack analysis, debugging setup and hold outliers, noise analysis,
scalability check and developing TCL and UNIX scripts to extract timing and noise reports.

Prime Time ToolTCLUNIXCode Quality ChecksNoise AnalysisStatic Timing Analysis

Moschip institute of silicon systems

Physical Design Trainee

May 2019 – Dec 2019 · 7 mos · India

Worked on PNR projects and have hands on experience in performing sanity checks, Design import, Floor planning, Power planning, Trail Route, Congestion Analysis, RC extraction, Timing Analysis, Clock Tree Synthesis, Detail Routing in both top level and block level designs. Also worked on running Logical Synthesis using ZWLM/WLM to achieve maximum frequency with different VT’s and have knowledge in standard cell designing.
Possess good working knowledge on Cadence Innovus , Genus, Tempus and Virtuoso.

PNR ProjectsSanity ChecksDesign ImportFloor PlanningPower PlanningCongestion Analysis+10