Mohammad Irfanullah — Software Engineer

I'm Irfanullah, an R&D Engineer at Synopsys Inc, with a Bachelor's degree in ECE (VLSI specialization) from KL University, India. ● Std Cell Characterization ●Good understanding of ASIC flow and the stages involved in physical design flow such as Netlist to GDSII. ● Digital Electronics ● Good understanding on all aspects of Physical Design including Synthesis, Floor Planning, PG Planning, IR Drop analysis, Congestion free Placement, Clock Tree Synthesis, Timing Closure, Routing and crosstalk. ● Good understanding of STA concepts such as Timing paths, setup and hold slack calculations, Common Path Pessimism, derating, techniques to fix setup and hold violations, multi cycle paths, half cycle paths, latch based timing analysis, MCMM, OCV ● Understanding of CMOS related concepts ● Interpreting timing reports ● Hands on experience with industry standard tools like Synopsys ICC, Cadence tempus, Innovus ● Verilog (Basic) ● Timing constraints in SDC ● Working Knowledge of Linux/Unix operating system

Stackforce AI infers this person is a Semiconductor R&D Engineer with expertise in ASIC design and physical design methodologies.

Location: Vijayawada, Andhra Pradesh, India

Experience: 2 yrs 11 mos