Mohit Agarwal — Product Engineer
Experienced ASIC PHY IP Verification Engineer with over 3+ years of hands-on experience in verifying complex semiconductor designs. Proficient in all aspects of verification methodologies, including test planning, testbench development, functional verification, and debugging. Skilled in using industry-standard verification languages and tools such as SystemVerilog, UVM, and VCS. Demonstrated ability to collaborate effectively with cross-functional teams to deliver high-quality ASIC designs on schedule. Strong analytical and problem-solving skills. Seeking to leverage expertise in ASIC verification to contribute to innovative semiconductor projects.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.
Location: Bangalore Urban, Karnataka, India
Experience: 7 yrs 10 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
Career Highlights
- 3+ years of experience in ASIC verification.
- Proficient in UVM and SystemVerilog.
- Strong analytical and problem-solving skills.
Work Experience
NVIDIA
Verification Engineer (1 yr 8 mos)
Synopsys Inc
ASIC Digital Design Engineer (3 yrs 4 mos)
Boeing
Project Intern (1 mo)
Indian Institute of Technology, Delhi
Summer Intern (2 mos)
Currents, NIT Trichy
Workshop Coordinator (2 yrs 9 mos)
The Third Dimension Aeromodelling Club
Tronics Member (2 yrs 10 mos)
Education
Bachelor of Technology at National Institute of Technology, Tiruchirappalli
Intermediate at Rajkamal Saraswati Vidya Mandir, Dhanbad