Navaneeth Krishna L S — Software Engineer

Dynamic VLSI Engineer with focused experience in Static Timing Analysis (STA), Timing Sign-Off, Timing Closure, Timing ECO and Physical Design. Proficient in Timing Constraints Development, Timing Exception Verification, Timing Analysis, and Timing Closure Methodologies. Skilled in using industry-standard EDA tools such as Cadence Genus, Cadence Innovus, Synopsys PrimeTime, Synopsys PrimeClosure, Synopsys Fusion Compiler and Tweaker. Demonstrated ability to ensure design integrity by meeting timing requirements while optimizing power and area constraints. Strong problem-solving abilities and attention to detail enable effective identification and resolution of timing issues. Collaborative team player with good communication skills, eager to contribute to innovative projects in the VLSI domain. Aiming for good professional growth and networking with industry peers.

Stackforce AI infers this person is a VLSI Engineer specializing in Static Timing Analysis and Physical Design.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 8 mos