Jan 2023 – Jan 2024 · 1 yr · San Francisco Bay Area · On-site

• Silicon Innovation & SoC Architecture Leadership
• 1. Founding Architect – SoC Architecture Group (SF Bay Area, Samsung Electronics)
• First hire and founding architect of the SoC Architecture group in the SF Bay Area, driving silicon innovation to enable AI/ML across XR/AR/VR, smartphones, laptops, and smartwatches. Secured funding from the MX CTO office to pioneer AI/ML acceleration within SoC architectures.
• 2. Team Scaling & Cross-Domain Expertise
• Grew the team to 25+ members, bringing in experts across SoC/system architecture, modeling, algorithms, and silicon characterization. Managed budgeting, hiring, and strategic planning.
• 3. Product-Driven SoC Architecture Methodology
• Promoted a product-centric approach to SoC, system, and software architecture. This starts with product vision and use-case identification, mapping to silicon IPs, firmware, system software, and applications.
• 4. ML/CV Architectural Innovation for XR/AR/VR Workloads
• Led innovation for advanced CV/ML workloads like head-eye-hand tracking, stereo depth estimation, plane detection, lighting modeling, mesh generation, super-resolution, LLaMA-7B inference, and vision transformers.
• 5. Architecture Modeling & KPI-Driven Feature Exploration
• Led development of architecture models correlated to silicon IPs, exploring features across CPU (L2/L3), graphics, neural engines, CV pipelines, display subsystems, media codecs, NoCs, cache, memory controllers, and MMUs.
• 6. Vendor Influence & Silicon Enablement for XR/VR
• Drove XR/AR/VR silicon vendors to address challenges like ultra-low latency camera-to-display pass-through, memory bandwidth optimization, and low-power real-time subsystems for concurrent neural and GPGPU processing.
• 7. Automotive Feature Exploration
• Investigated SoC enhancements for adapting mobile and XR architectures to automotive domains (ADAS and infotainment), laying the groundwork for business opportunities and cross-segment silicon reuse.

Jan 2020 – Jan 2023 · 3 yrs · On-site

• Leadership in Data Center AI Training SoC & Platform Architecture
• 1. Architected Next-Gen AI Training SoC – Led Product and SoC Architecture for Data Center AI Training, leveraging a multi-die package with Foveros & EMIB. Designed functional die segregation: X86 (CPU), Xe (GPU), Memory Controller, Fabric, SoC, stacked memory layer, and IO, optimizing compute and memory performance.
• 2. Technical Leadership in Distributed AI Compute – Directed System & SoC architecture for distributed shared memory models, ocean-of-compute connectivity (proprietary H-RoCE), and host interfaces (CXL 3.0, PCIe Gen 6). Enabled dedicated CXL expansion memory for GPUs, enhancing scalability and performance.
• 3. Microarchitecture & System Scalability – Led microarchitectural innovation across fuse distribution, telemetry, confidential compute, power management, reliability, serviceability, secure boot, and debug. Defined a highly scalable coherent fabric (>8 TB/s) and ordered fabric (>0.5 TB/s – PCIe Gen 6) alongside a HBM + DDR memory subsystem and 3D memory-based system cache.
• 4. Firmware & Software Ecosystem Leadership – Defined firmware components, functionality, and flows across the SoC, collaborating with software architects to optimize system and driver implementations (PCIe/CXL modes, page tables, virtualization, telemetry, and H-RoCE). Spearheaded debug tools (VTune) for SoC performance profiling.
• 5. Process, Package & Platform Innovation – Engaged with process & package technologists and structural design teams to optimize per-die process nodes and package integration. Led platform solutions for Ethernet switches, system manageability, and scale-up/scale-out networking.
• 6. Resolved Complex SoC Architecture Challenges – Drove critical SoC issue resolution, including cross-die data flows, Linux/Windows boot, DMA engines, access control, address decoding, and hashing, ensuring a robust AI training solution.

Jan 2019 – Jan 2023 · 4 yrs · On-site

• Client SoC and Product Architecture leadership
• 1. End-to-End Product & SoC Architecture Leadership – Led product definition, ecosystem enablement (Chrome, Windows OS), and SoC execution, driving integration and alignment with platform requirements.
• 2. Strategic Architectural Exploration – Spearheaded exploration of architectural options including SKU segmentation, die disaggregation, internal vs. external IPs, market adjacency strategies, and competitive differentiation (5G/LTE, memory compression). Collaborated with marketing to define highly competitive SoC roadmaps (2023-2026) across multiple scenarios:
• Foundry Options: Intel, TSMC, Samsung
• Packaging Strategies: Intel or outsourced
• IP Integration: External, internal, or hybrid approach
• SoC Chassis Strategy: Leverage existing infrastructure vs. new architecture
• 3. Ownership of Cost, Execution, & Specifications – Directed a cross-functional team responsible for die area, ASIC cost, solution BOM, R&D cost, execution schedule, architecture specifications, and SoC integration requirements, ensuring cost-effective and competitive solutions.
• 4. Performance & AI Use-Case Optimization – Led technical decomposition of key benchmarks and power-perf analysis, ensuring feasibility for concurrent and AI-driven workloads while optimizing power efficiency.
• 5. Leadership on SoC IP Domains – Built and led a team of domain experts across Neural (AI/ML) engines, Graphics (3D/2D), Media codecs, Display, Imaging, High-Speed IOs, Sensors, Audio, Security, Debug, Compression, Connectivity (WiFi, Bluetooth, 5G/LTE), Power Management, Clocking, CPU Config, System Cache, and Interconnect (chassis for Intel IPs).
• 6. Technical & Business Alignment – Technical guidance for financial negotiations with IP design and SoC vendors. Supported project management in tracking deliverables across key stakeholders like IP design, Chrome/Windows driver development, functional modeling, power-perf analysis, and SoC integration.

Jan 2019 – Jan 2021 · 2 yrs · On-site

• Advanced SoC Disaggregation & Chiplet Integration
• 1. Strategic Disaggregation & 3D Integration – Evaluated multiple disaggregation approaches (EMIB, Foveros, silicon interposers) based on power, performance, area, cost, scalability, and technology roadmap. Enabled 3D-stacked memory integration, delivering >384MB cache for integrated graphics in client SoCs.
• 2. Die-to-Die IP Leadership – Architected and implemented a protocol-agnostic die-to-die (D2D) interconnect, optimizing for minimal latency, power, and area while ensuring independent clocking, power management, and cross-die scalability. First-generation D2D IP tunneled five protocols (IDI, iCXL, CMI, DDI, IOSF) across 16 links and 5 dies, enabling a high-bandwidth, multi-die package.
• 3. Next-Gen SoC Innovations – Defined next-gen architectural enhancements, including Data Bus Inversion, variable voltage rails, enhanced reliability/yield, lower power via shallower shorelines, elimination of dedicated D2D PLLs, and credit-based link-level flow control, driving efficiency, performance, and manufacturability.

Jan 2019 – Jan 2021 · 2 yrs · On-site

• Driving Silicon Innovation for Intel Evo Platforms
• 1. Architected Next-Gen Silicon Solutions – Led development of Intel Evo companion die solutions, strategically segregating features across swim lanes to optimize performance, power, and cost across product tiers.
• 2. Strategic Partner Engagement – Drove design service partner selection, engagement, and onboarding, ensuring alignment with Intel’s silicon innovation roadmap.
• 3. Product Definition & SoC Architecture – Developed product specifications, SoC architecture strawman, and RFQ documents, providing a structured framework for execution.
• 4. Innovative Low-Power AV Solutions – Spearheaded low-power audio/video innovations tailored for Intel Athena/Evo platforms, enhancing user experience and energy efficiency.
• 5. Market Differentiation – Strategically segregated premium and mainstream features, ensuring clear differentiation while maintaining cost efficiency across product tiers.

Jan 2017 – Jan 2019 · 2 yrs · San Francisco Bay Area · On-site

• System & SoC Architecture Leadership
• 1. Scalable, Low-Latency Ethernet Interconnect – Defined system architecture and microarchitecture for a resilient, congestion-aware Ethernet fabric with load balancing, rate throttling, RTT estimation, link aggregation, and secure link management.
• 2. Secure System Boot & Management – Architected reset, initialization, and system management over 1/10Gbps Ethernet, ensuring secure communication with management hosts.
• 3. FPGA Implementation & IP Integration – Directed FPGA setup and Vivado IP configurations, including CMAC, SerDes, PCIe Gen4x8, HBM PHY/Controller, NoC, KP4-FEC, EMAC, QDMA, SHA/AES, and MicroBlaze subsystems.
• 4. Next-Gen Z1-ASIC Architecture – Designed future Z1-ASIC, supporting 2-4 stacks of HBM3 (16-64GB), dual PCIe Gen4x16 endpoints, 144x112Gbps serial links, 12x100Gbps Ethernet controllers, multi-TB/s NoC, A75 Quad-core, and a secure boot subsystem.
• 5. System Card Architecture – Led component evaluations and system card design, featuring XCVU37P FPGA, PCIe switch, 400Gbps gearbox, QSFP-DD, cabled PCIe Gen4x8, and high-speed backplane connectors.
• 6. Ultra-High-Speed Serial Link Design – Defined architecture based on use case-driven requirements (28/56/112Gbps, PAM-4/NRZ, BER, RS-FEC, CRC-protected FEC, virtual channel flow control, and signaling/recovery modes).
• 7. CNN Engine Optimization for AI Vision – Spearheaded camera image capture & inference analysis, specifying CNN engine features (Sigmoid, Tanh, ReLU) and solving thermal hot-spotting via architectural and floorplan enhancements.
• 8. ADAS & Infotainment SoC Leadership – Decomposed end-to-end ADAS & infotainment use cases (sensor fusion, ML, perception, planning) to drive next-gen FSD-4.0 ADAS-SoC architecture, covering process node selection, IP definition, NoC configuration, secure boot, power management, and floor-planning.

Jan 2012 – Jan 2017 · 5 yrs · San Francisco Bay Area · On-site

• Technical Leadership in Memory Subsystem & SoC Architecture for Apple products
• 1. Pioneered Memory Subsystem Architecture for the first-generation Apple Watch SoC, defining memory controller features, SoC integration, and performance optimization. Led critical silicon debug efforts, ensuring first-pass success.
• 2. Drove Next-Generation SoC Innovations by architecting QoS-based traffic shaping for the memory controller scheduler, enabling predictable performance under complex workloads.
• 3. Led Memory Architecture Exploration for LPDDR4/4E, evaluating cache strategies, Tags-in-RAM, and non-volatile memory to enhance power efficiency and responsiveness.
• 4. Architected Advanced Calibration Algorithms, optimizing periodic read, write, Vref, Data Strobe, and Master DLL calibrations, ensuring minimal error bounds, reduced calibration delays, and power-efficient frequency transitions.
• 5. Designed High-Impact Performance Features, including segmented memory calibration, dynamic frequency/voltage scaling, cross-channel alignment, refresh scheduling, and seamless PHY-to-Memory Controller handshake for real-time traffic management.
• 6. Innovated System-Level Resource Management, leading the Retry Handling Queue and Tag Pipeline architecture, optimizing system cache, CPU caches, and memory controller efficiency through advanced replacement policies, flush handling, and power-aware way management.

Jan 2007 – Jan 2012 · 5 yrs · San Francisco Bay Area · On-site

• High-Performance Networking & SoC Subsystems
• 1. Architected and Developed a High-Efficiency FIFO Controller, achieving 99% utilization for 2048-queue Ethernet traffic management using DDR3 storage. Led DDR3 PHY integration, feature selection, and compatibility with Samsung and Micron memory solutions.
• 2. Led SoC Subsystem Memory Architecture, driving feature selection and integration of a 32-bit DDR3 PHY and AXI-based DDR3 controller IP, optimizing memory throughput and system performance.
• 3. Developed AXI Fabric Automation, creating a script-driven synthesis flow to generate and explore AXI fabric architectures, accelerating design iteration and optimization.
• 4. Designed and Optimized Ethernet Port Macro, supporting multi-speed (10G/2.5G), aggregation (10/40/100G), and multi-lane (1,2,4,10) configurations, ensuring high-performance scalability.
• 5. Led Micro-Architecture and Integration of SerDes IP, developing RTL for lane swapping, clock/power management, PLL tuning, timers, register access (MDIO, Micro-8051), and firmware-driven timer synchronization.
• 6. Drove Security & Networking IP Integration, selecting and integrating Ethernet IP into MacSec, architecting CAM-based lookups for 4-port MacSec, and designing high-efficiency Security/RMON counters leveraging optimized memory structures.
• 7. Owned End-to-End Design Flow & Delivery, overseeing synthesis, STA, lint checks, clock domain crossing, chip integration, and verification, ensuring first-pass silicon success.
• 8. Championed Industry Standards & Energy Efficiency, leading specification and RTL development of Energy Efficient Ethernet (EEE) for 10G BASE-KR PCS, providing expert feedback to IEEE standard committees.

Jan 2004 – Jan 2007 · 3 yrs · Bangalore, India and San Francisco Bay Area · On-site

• Key Responsibilities & Impact:
• 1. Drive ownership of functional and micro-architecture specifications, ensuring alignment with project requirements.
• 2. Develop high-performance RTL designs (ASIC/FPGA) tailored to project needs.
• 3. Architect and implement SystemVerilog-based verification environments, enabling robust pre-silicon validation.
• 4. Define and execute comprehensive test plans, leveraging simulation testbenches, RTL models for PHY/SoC, and advanced protocol checking toolkits.
• 5. Lead SoC integration, Design Compiler synthesis, and FPGA implementations (Xilinx/Altera) to meet performance and power targets.
• 6. Spearhead silicon validation and lab bring-up, ensuring seamless interoperability with industry devices and FPGA platforms.