Nitty Thomas

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience
Highly Stable

Key Highlights

  • Expertise in Physical Design Engineering.
  • Proficient in ASIC and SoC design methodologies.
  • Strong background in RTL Design and Static Timing Analysis.
Stackforce AI infers this person is a Physical Design Engineer specializing in ASIC and SoC technologies.

Contact

LinkedIn

Skills

Other Skills

VerilogApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)Field-Programmable Gate Arrays (FPGA)CMicrosoft OfficeMicrosoft WordPerlStatic Timing AnalysisLow-power Designsystem verilogRTL DesignTCL

Experience

8 yrs 9 mos
Total Experience
8 yrs 9 mos
Average Tenure
8 yrs 9 mos
Current Experience

Mediatek

4 roles

Staff Engineer

Jun 2022 – Present · 3 yrs 11 mos

Senior Physical Design Engineer

Promoted

Jun 2019 – Jun 2022 · 3 yrs

Physical Design Engineer

Jul 2018 – Jun 2019 · 11 mos

Graduate Technical Intern

Jul 2017 – Jun 2018 · 11 mos

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI

Jan 2016 – Jan 2018

Rajagiri School of Engineering and Technology, Rajagiri Valley P.O, Kakkanad, Kochi- 682 039

Bachelor of Technology - BTech — Electronics and Communication Engineering

Jan 2011 – Jan 2015

Stackforce found 100+ more professionals with Verilog & Application-Specific Integrated Circuits (ASIC)

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